tag: Synopsys

Artificial Intelligence: Let Us Get The Math Right First!
By Ravindra Aneja - 06 Jun, 2019 - Comments: 0

Artificial intelligence is a hot topic these days and therefore doesn’t require a repeat of the current and future potential uses for AI. For most people, it means technology advancements on the software side. But if you ask people who are very close to this technology domain, building your own optimized hardware chips is where a significant part of the competitive edge lies. A few days ba... » read more

Machine Learning Drives High-Level Synthesis Boom
By Kevin Fogarty - 06 Jun, 2019 - Comments: 0

High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts. The obvious advantage of HLS is the boost in productivity designers get from working in C, C++ and other high-level languages rather than RTL. The ability to design a layout that should work, and then easily modify it to test other confi... » read more

Holes In AI Security
By Ed Sperling - 06 Jun, 2019 - Comments: 0

Mike Borza, principal security technologist in Synopsys’ Solutions Group, explains why security is lacking in AI, why AI is especially susceptible to Trojans, and why small changes in training data can have big impacts on many devices. » read more

Securing The Mobile IoT
By Synopsys - 05 Jun, 2019 - Comments: 0

It’s 2019. Security fears, locked ecosystems, and lack of technology are keeping IoT products within WiFi networks, and not reaching their full potential. As an industry, we must provide IoT solutions that are simple and keep consumers--and their data--secure.The mobile IoT is the next frontier in the connected device market, providing out-of-the-box connectivity with security from silicon... » read more

Training Tomorrow’s Chip Designers
By Ann Mutschler - 05 Jun, 2019 - Comments: 1

With technology advancing rapidly and the growing number of open R&D projects, there is an expanding need for qualified engineers. To make this possible, practical education needs to start much earlier than after graduation. One the best ways the EDA and semiconductor industry has embraced is encouraging engineering students to cooperate with experienced engineers, technologists and indu... » read more

Using Synopsys Z01X To Accelerate The Fault Injection Campaign Of A Fully Configurable IP
By Arteris - 05 Jun, 2019 - Comments: 0

By Arteris IP Alexis Boutillier, Corporate Application Manager, Safety Manager, and Mohan Krishnareddy, Solution Engineer, at the Synopsys Users Group (SNUG), March 2018, Santa Clara, CA. Principles and real-world practices of ISO 26262 for semiconductor design teams. After providing an overview of how functional safety affects management, development, and supporting processes, the paper exp... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2019 - Comments: 0

Mentor's Neil Johnson argues that coverage closure shouldn't have to be mad scramble in the home stretch of development if designers change their early development mindset. In a video, Cadence's Amol Borkar explains Simultaneous Localization and Mapping, or SLAM, from the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Synopsys' Tay... » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 May, 2019 - Comments: 0

M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

Shift-Left Low Power Verification With UPF Information Model
By Himanshu Bhatt - 30 May, 2019 - Comments: 0

By Himanshu Bhatt, Shreedhar Ramachandra and Narayanan Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power testbenches that can monitor the UPF objects and react to the state changes of UPF objects. To meet this requirement for the user to... » read more

How To Integrate An Embedded FPGA
By Brian Bailey - 30 May, 2019 - Comments: 1

Choosing to add programmable logic into an SoC with an eFPGA is just the beginning. Other choices follow involving how many lookup tables (LUTs), how much routing and what topology, how will data be transferred in and out of the fabric, does data need to be coherent with system memory, how will it be programmed and tested, and what RTL functions need to be embedded into the programmable fabric ... » read more

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