tag: Synopsys

Big Shift In Multi-Core Design
By Ann Mutschler - 03 Apr, 2019 - Comments: 0

Hardware and software engineers have a long history of working independently of each other, but that insular behavior is changing in emerging areas such as AI, machine learning and automotive as the emphasis shifts to the system level. As these new markets consume more semiconductor content, they are having a big impact on the overall design process. The starting point in many of these desig... » read more

Safety Critical Design In Automotive
By Ed Sperling - 03 Apr, 2019 - Comments: 0

Shiv Chonnad, hardware engineer at Synopsys, examines how to design chips for safety-critical applications such as automotive and ensure they work as planned and in accordance with ISO 26262 and the various ASIL levels. This includes how to find faults at both a chip and a system level. https://youtu.be/3dL4ZuSe5Ls » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 29 Mar, 2019 - Comments: 0

Internet of Things Organizers for the Internet of Things World 2019 conference, coming up on May 13-16 in Santa Clara, Calif., surveyed more than 100 IoT leaders in various industries. Implementation (34%) and security (25%) were the highest concerns for the respondents. Those were followed by initial purchase (17%), scalability (10%), business buy-in (8%), and upkeep costs (3%). Two-thirds of... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Mar, 2019 - Comments: 0

ON Semiconductor will acquire Quantenna Communications for $24.50 per share in an all cash transaction, representing an equity value of approximately $1.07 billion and enterprise value of approximately $936 million. Quantenna, a maker of Wi-Fi chipsets, was founded in 2006 and went public in late 2016. Tools & IP Achronix completed testing and is now demonstrating the 112 Gbps SerDes th... » read more

Building Bridges: A New DFT Paradigm
By Robert Ruiz - 28 Mar, 2019 - Comments: 0

Over the last twenty years, structural testing with scan chains has become pervasive in chip design methodology. Indeed, it’s remarkable to think that most electronic devices we interact with today (think smartphones, laptops, televisions, etc.) contain hundreds to thousands of interconnected scan chains used to verify that the semiconductors were manufactured without defects. Because the imp... » read more

Digital Twins Deciphered
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Ever since Siemens acquired Mentor Graphics in 2016, a new phrase has become more common in the semiconductor industry – the digital twin. Exactly what that is, and what impact it will have on the semiconductor industry, is less clear. In fact, many in the industry are scratching their heads over the term. The initial reaction is that the industry has been creating what are now termed digi... » read more

Utilizing More Data To Improve Chip Design
By Ann Mutschler - 28 Mar, 2019 - Comments: 0

Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out what's important for which parts of the design flow. That determines what to extract and loop back to engineers, and when that needs to be done in order to improve the reliability of increasingly com... » read more

The Automation Of AI
By Brian Bailey - 28 Mar, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained Parallelism
By Synopsys - 27 Mar, 2019 - Comments: 0

Non-stop growth in design size and complexity makes it more difficult than ever for verification teams to keep up with project demands and product goals. According to the Synopsys 2017 Global User Survey, “Verification taking longer than planned” is the top reason for tapeout delays, and “Simulation runtime performance” is the top challenge for verification. Since regression test turn-a... » read more

Debug Changes At Advanced Nodes
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a commensurate amount of software complexity. The key is how to maintain or reduce time to market, and that requires a different way of approaching the problem. » read more

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