Blog Review: Oct. 8


Siemens' Azat Latypov presents a stochastic-aware optical proximity correction strategy that demonstrated an order-of-magnitude reduction in the probability of stochastic defects for both SRAM and logic designs, sacrificing minor edge placement error in return for much lower failure rates. Cadence's Dimitry Pavlovsky introduces the AMBA CHI Chip-to-Chip (C2C) protocol, which extends the CHI ... » read more

How 3D-IC Will Change Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

Chip Industry Week in Review


Samsung and SK hynix joined OpenAI's Stargate initiative to ensure there will be enough memory chips to meet the needs of AI data centers. The goal is to produce up to 900,000 DRAM wafer starts per month. OpenAI also inked agreements to explore the development of next-gen data centers in Korea. Axcelis Technologies (ion implantation systems) will merge with Veeco Instruments (compound semic... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control


When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Blog Review: Oct. 1


Synopsys' Chun-Soo Kim and Hoseong Kim suggest making the entire design flow local layout effect-aware to identify and address issues early and ultimately improve PPA by avoiding overly pessimistic designs. Siemens' Kirk Fabbri explores the power distribution network, focusing on power plane capacitance and how it varies with the dynamic switching characteristics of the load and dielectric c... » read more

How To Cool 3D-ICs


Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what's missing from the tool chain today, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysigh... » read more

Chip Industry Week In Review


U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

Navigating The Challenges Of Group Design Projects


All over the world, governments and industry have come together to solve large-scale chip design challenges. Groups such as the U.S. Department of Defense’s Microelectronics Hubs (ME Commons), the EU Chips Act pilot lines, and Japan’s government-backed Rapidus consortium often consist of established companies, research institutes, academia, and startups – each of which brings different sk... » read more

The Limits Of AI’s Role In EDA Tools


The world has been inspired by generative AI models like ChatGPT. These are very applicable to things like copilots and agentic AI, but the adoption of these models into EDA tools is less obvious. What may be appropriate, and can AI make EDA tools faster or better? EDA has been enabling Moore's Law for the past 40 years, and that has required pushing the limits of many of the algorithms and ... » read more

First Forays Into True 3D-IC Designs


Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

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