The Future Of Verification


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Blog Review: Sept. 24


Siemens' Harry Foster warns of a big drop in first-time silicon success as more system companies tackle developing their own chip without the accumulated knowledge around flows, sign-off criteria, and coverage closure in a landscape where even small oversights in methodology can lead to multimillion-dollar respins. Synopsys' Godwin Maben warns that skyrocketing power consumption is a critica... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Chip Industry Week in Review


Amkor, TSMC, and Cadence partnered with Tesoro VC, which will serve as the lead operator of a new Global AI + Semiconductor Startup Hub and a Global Design Center in Phoenix, Arizona, aimed at chip innovation, startup growth, and advanced manufacturing. Nvidia will invest $5 billion in Intel common stock at a purchase price of $23.28 per share and the companies will collaborate on AI infrastru... » read more

Quantum Computing: How Advances May Reshape Our Understanding Of The World


After decades spent gestating in labs, quantum computing has finally reached an inflection point between theoretical promise and practical implementation. From discoveries in pharmaceutical and material sciences to boosting artificial intelligence (AI) and climate modeling, quantum computing is on the cusp of providing an entirely new way to solve highly complex problems — which could ultimat... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging


In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Glass Substrates Gain Momentum


As a package substrate, the benefits of glass are substantial. It's extremely flat with lower thermal expansion than organic substrates, which simplifies lithography. And that's just for starters. Warpage, a growing problem for multichip packages, is greatly reduced. Chips can be hybrid bonded to redistribution layer pads on glass. And relative to organic-core substrates, glass provides very... » read more

Simulating Atomic Layer Processing Of 2D Materials


Integrating 2D materials into sustainable electronic devices presents key challenges, particularly in depositing or etching nanometer-thick layers on high aspect ratio structures. Atomic Layer Etching (ALE) offers atomic-level precision and has demonstrated success in producing atomically thin layers of transition metal dichalcogenides (TMDs) like MoS2. Synopsys has developed an industry-grade ... » read more

New Demands For IP Reuse


Experts at the Table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight;... » read more

Blog Review: Sept. 17


Siemens' John McMillan explores the fundamentals of IC package thermal resistance, modeling strategies, and why die-level thermal analysis in 3D-ICs is increasingly essential for ensuring device reliability. Cadence's Jasmine Makhija provides an overview of the TEE Device Interface Security Protocol (TDISP), which helps safeguard PCIe devices within Trusted Execution Environments by providin... » read more

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