tag: Synopsys

Don’t Let Bad Apples Ruin Your Pie
By Synopsys - 21 Dec, 2016 - Comments: 0

The quality of a pie depends heavily on the ingredients you use. Do you use bleached white flour or organic multigrain flour? Do you use sugar or a carcinogenic artificial sweetener? Do you use Granny Smith apples, or Honeycrisp, or those funky apples that fell off the tree that’s in your neighborhood? Managing ingredients is crucial to your success. Suppose you’re not paying close atten... » read more

Blog Review: Dec. 21
By Jesse Allen - 21 Dec, 2016 - Comments: 0

Mentor's Jeff Miller and ARM's Nandan Nayampally contend that it's easier than ever to design custom SoCs. Cadence's Paul McLellan provides a basic primer on silicon photonics, from a presentation by Gilles Lamant. The US Department of Transportation is considering requiring the inclusion of vehicle-to-vehicle communication in new cars, says Synopsys' Robert Vamosi. Applied's Shekar Kr... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2016 - Comments: 0

What are the technology options for 5nm? Cadence's Paul McLellan highlights an IEDM presentation by An Steegen of Imec. Synopsys' Michael Posner suggests we may not have to live with USB Type-C dongles for very long. Mentor's Craig Armenti presents some of the fundamental best practices and guidelines for rigid-flex PCB design. NXP's Joe Byrne digs into the Mirai botnet attack, arguing... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 14 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Formal’s Roadmap
By Brian Bailey - 12 Dec, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

The Week In Review: Design
By Jesse Allen - 09 Dec, 2016 - Comments: 0

Standards The latest version of the Bluetooth standard was ratified by the Bluetooth Special Interest Group. Key updates in Bluetooth 5 include four times range, two times speed, and eight times broadcast message capacity, as well as updates that help reduce potential interference with other wireless technologies. Tools Synopsys updated its hierarchical static timing analysis tool for ... » read more

Embedded Software Verification Issues Grow
By Ann Mutschler - 08 Dec, 2016 - Comments: 0

Embedded software is becoming more critical in managing the power and performance of complex designs, but so far there is no consensus about the best way to approach it—and that's creating problems. Even with safety-critical standards such as DO-178C for aerospace and [gettech id="31076" comment="ISO 26262"] for automotive, different groups of tool providers approach software from differen... » read more

Tuning Heterogeneous SoCs
By Brian Bailey - 08 Dec, 2016 - Comments: 0

It's one thing to pack multiple processor cores into a design, but it is much more difficult to ensure the hardware matches the software's requirements, or that the software optimally uses the hardware. Both the hardware and software teams are now facing these issues, and there are few tools to help them fully understand the problems or to provide solutions. Design teams continue to add more... » read more

Analog’s Rising Status
By Ann Mutschler - 08 Dec, 2016 - Comments: 1

As more sensors and actuators are added into electronic devices, pressure is growing to more seamlessly move data seamlessly back and forth between analog and digital circuitry. [getkc id="37" kc_name="Analog"] and digital always have fit rather uncomfortably together, and that discomfort has grown as [getkc id="81" kc_name="SoCs"] are built using smaller feature sizes. While digital transis... » read more

Ensure Robust Encryption With CAVP Validation For FIPS 140-2 Conformance
By Derek Bouius - 08 Dec, 2016 - Comments: 0

Cryptographic algorithms are mathematical procedures used to implement security protocols in today’s devices and communication infrastructure. Designers must validate their cryptographic algorithm implementations through certification by regulatory bodies, such as Communications Security Establishment Canada (CSEC) and National Institute of Standards and Technology (NIST), to ensure accuracy ... » read more

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