tag: verification

Do Chips Really Work The First Time?
By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

The Other Side Of Formal
By Joseph Hupcey III - 13 Feb, 2014 - Comments: 1

It’s natural to think of formal analysis as a ruthlessly effective bug hunter and verification tool. But as the following case study from Homayoon Akhiani, presented at the Jasper Users Group (JUG) meeting shows, customers are using this approach to increase their SoC’s performance in ways that are very visible to the end-user of the part. Such visible improvements — in this case, minimiz... » read more

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
By Karthik Srinivasan - 13 Feb, 2014 - Comments: 0

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

The Growing Verification Challenge
By Ed Sperling - 30 Jan, 2014 - Comments: 1

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

Billion-Gate Signoff
By Graham Bell - 30 Jan, 2014 - Comments: 0

At last year’s Design and Verification Conference in San Jose, Real Intent had a tutorial session on “Pre-Simulation Verification for RTL Sign-Off.” This was a start of conversation in the industry that we have seen grow through DAC 2013 in Austin, and which is getting louder each day. Verification companies are now talking about crossing the billion-gate threshold and what can be done to... » read more

10 Years Later—Will Project Delays Stop Faster Technology Innovation?
By Frank Schirrmeister - 29 Jan, 2014 - Comments: 0

Every January I enjoy looking back 10 years to learn from the past, consider implications for the future, and have fun picking the worst prediction that did not come true. This year I even can combine my annual trip to the garage where I keep some January issues of IEEE Spectrum with reviewing my own blogging. Five years ago in 2009, I did my first “10-year-lookback” that I called “Bac... » read more

Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
By Various Writers - 29 Jan, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

2014 Accellera Standards Are Built on Powerful Shoulders
By Accellera - 27 Jan, 2014 - Comments: 0

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

Tech Talk: Changes In Verification
By Ed Sperling - 27 Jan, 2014 - Comments: 0

Roger Hughes, director of strategic accounts at Real Intent, talks about what's changing in verification as design complexity increases and where engineers typically make mistakes. [youtube vid=0SE97LvCilo] » read more

Power’s Impact On Hierarchy Modification
By Ann Mutschler - 16 Jan, 2014 - Comments: 2

RTL restructuring in which the logical hierarchy of a design is modified is usually done to manage complex designs. When power management is added to this task, new challenges crop up. Consider switchable power or voltage domains, which are a common way to manage power is to use switchable power or voltage domains. When implementing this technique, all the logic in such a domain must hang of... » read more

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