tag: verification

Tech Talk: Dealing With The Unknowns
By Ed Sperling - 15 Jan, 2014 - Comments: 0

Rebecca Lipon, senior product marketing manager for verification at Synopsys, discusses the problematic X's and where verification teams typically make mistakes in trying to eliminate the false X's from their designs. Power emerges as the biggest problem. [youtube vid=Iym4ITWJJrs] » read more

How to Achieve Estimation, Reduction, And Verification Of Power In RTL Designs
By Various Writers - 15 Jan, 2014 - Comments: 0

Maintaining power dissipation at low levels is a major concern in modern day IC designs. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and is an effective differentiator. Mobile phones, digital cameras and personal MP3 players are increasingly being sold based on their battery lives. In wired applications, power consumption determines ... » read more

Blog Review: Jan. 15
By Ed Sperling - 15 Jan, 2014 - Comments: 0

Mentor’s Colin Walls digs into safety-critical sensors for cars, which are essential to the operation of a variety of systems in vehicles. The number of redundant sensors increases proportionate to the risk from failure, something that has been an accepted practice in mil/aero markets for years. Cadence’s Brian Fuller gazes into a crystal ball and concludes that while the semiconductor i... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Blog Review: Jan. 8
By Ed Sperling - 08 Jan, 2014 - Comments: 0

How do you choose an embedded operating system—and do you even need one? Mentor’s Colin Walls looks at the options, and the reason why there are no simple answers. Cadence’s Richard Goering has evidence that Facebook is gaining in popularity for engineer. He’s not the first person to recognize this shift, but the big unanswered questions are, ‘What’s the average age of those use... » read more

Blog Review: Jan. 2
By Ed Sperling - 02 Jan, 2014 - Comments: 0

ARM’s Lori Kate Smith has been scouring the market for cool devices. Her pick: the Epic Giveaway wrist computer for runners. She says the only drawback is the 10-hour battery life, but if you can run that long and still have some juice left in your body you probably need a GPS, instead. Mentor’s J VanDomelen has been tracking orders from the United Arab Emirates’ and its neighbors for ... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Top 5 Trends For 2014
By Frank Schirrmeister - 19 Dec, 2013 - Comments: 0

My daughter’s and my traditional yearly cookie baking party last weekend reminded me of two things: There is still no easy recipe for system design and verification and – of course – the year is almost over again. Ouch. Let’s look back at 2013 first. Earlier this year we held a System to Silicon Verification Summit in San Jose, with an interesting technical keynote by Brian Bailey an... » read more

Accelerating Functional Closure
By Various Writers - 18 Dec, 2013 - Comments: 0

This paper focuses on practical aspects of the verification process that can help reduce the time taken to reach functional closure. It is based on experiences of working directly with many leading edge semiconductor companies implementing modern verification technologies and methodologies. Since coverage is a measure of how effectively the design is being verified, this paper will address when... » read more

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics
By David Hsu - 05 Dec, 2013 - Comments: 0

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confi... » read more

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