tag: verification

Innovating Virtualization In Emulation
By Frank Schirrmeister - 24 Nov, 2015 - Comments: 0

Last week we officially introduced our next-generation emulator. We used the words “datacenter” and “virtualization” a lot, and it is worthwhile to underline the significance of what just happened in emulation. The new concepts are just as key to emulation as was the invention of virtual memory and memory management units to processors and software development. The concept of virtual... » read more

Defining Sufficient Coverage
By Brian Bailey - 24 Nov, 2015 - Comments: 2

Semiconductor Engineering sat down to discuss the definition of sufficient coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"], Larry Vivolo (who at the time of this roundtable was senior director of product marketing for [gete... » read more

ARM Cortex SoC Prototyping Platform For Industrial Applications
By Aldec - 23 Nov, 2015 - Comments: 0

Modern industrial systems are faced with many key design challenges including: system complexity, real-time performance requirements, evolving standards, and rising costs. ASIC prototyping platforms, such as the Aldec HES-7, provide a platform for designers to implement and verify functionality of industrial systems at-speed prior to silicon tape-out, saving money from costly re-spins. In this ... » read more

You’re Not Alone
By Srinivas Velivala - 19 Nov, 2015 - Comments: 0

All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from... » read more

One Flow To Rule Them All
By Brian Bailey - 12 Nov, 2015 - Comments: 0

The new mantra of shift left within EDA is nothing new and first made an appearance more than a decade ago. At that time there was a very large divide between logic synthesis and place and route. As wire delays became more important, timing closure became increasingly difficult with a logic synthesis flow that did not take that into account. The tools subsequently became tied much closer togeth... » read more

Enhancing Automotive Electronics Reliability Checking
By Mentor, a Siemens Business - 11 Nov, 2015 - Comments: 0

While complexity in the automotive electronics space continues to increase, ensuring reliability in safety-critical systems is crucial to the success and reputation of the automotive industry. Automation of complex reliability verification tasks provides a robust and repeatable mechanism for building reliable automotive IC designs within market-driven schedules. Utilizing advanced reliability v... » read more

Stop Getting Burned By Power Consumption Surprises
By Alan Gibbons - 09 Nov, 2015 - Comments: 0

Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issue... » read more

The Cloud, The IoE, And You
By Ernest Worthman - 05 Nov, 2015 - Comments: 0

If you’re anywhere in the high-tech biz, the two terms that are rocking your world are the Internet of Everything and the Cloud. Whether you are on the inside track of these, or on the sidelines, they are going to be two of the most disruptive technologies of the 21st century. The cloud is already here and gaining momentum. Some people will argue that the cloud has been here since the ince... » read more

SoC Verification For The Internet of Things
By Mentor, a Siemens Business - 04 Nov, 2015 - Comments: 0

Larger, more complex designs with more software and tighter power budgets require new verification solutions that target the associated technological challenges. This paper explores why traditional digital simulation and hardware prototypes fall short when it comes to verifying IoT and network designs, why using emulation is critical for a total verification solution, and why traditional in-cir... » read more

The New Face of Formal
By Brian Bailey - 04 Nov, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the recent growth in adoption of formal technologies and tools with Lawrence Loh, product engineering group director at [getentity id="22032" e_name="Cadence"], Praveen Tiwari, senior manager R&D, verification group at [getentity id="22035" e_name="Synopsys"], Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Normando... » read more

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