tag: advanced packaging

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Collaboration Widens Among Big Chip Companies
By Ed Sperling - 23 Jan, 2023 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the growing need for collaboration among equipment and tools vendors, the impact of systems companies and increases in complexity, and how to handle a push for more customization while controlling costs, with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computati... » read more

An OSAT Perspective On Semiconductor Market Trends
By Vik Chaudhry - 19 Jan, 2023 - Comments: 0

For the semiconductor industry, 2022 was a very interesting year. On one hand, it witnessed shortages in the supply chain. On the other hand, the macro-economic situation turned and demand for several consumer and computing devices plummeted. A trade war with China and ensuing localization of supply chain with passage of CHIPS act took shape in 2022. The auto industry is still recovering from t... » read more

Unknowns And Challenges In Advanced Packaging
By Ed Sperling - 19 Jan, 2023 - Comments: 0

Dick Otte, CEO of Promex Industries, sat down with Semiconductor Engineering to talk about unknowns in material properties, the impact on bonding, and why environmental factors are so important in complex heterogeneous packages. What follows are excerpts of that conversation. SE: Companies have been designing heterogeneous chips to take advantage of specific applications or use cases, but th... » read more

Design And Verification Methodologies Breaking Down
By Brian Bailey - 12 Jan, 2023 - Comments: 0

Tools, methodologies and flows that have been in place since the dawn of semiconductor design are breaking down, but this time there isn't a large pool of researchers coming up with potential solutions. The industry is on its own to formulate those ideas, and that will take a lot of cooperation between EDA companies, fabs, and designers, which has not been their strong point in the past. It ... » read more

Looking Inside Of Chips
By Ed Sperling - 10 Jan, 2023 - Comments: 0

Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

Heterogeneous Integration Issues And Developments
By Ed Sperling - 14 Dec, 2022 - Comments: 0

There are a slew of new developments in advanced packaging, from new materials, chiplets, and interconnect schemes, to challenges involving how to physically put chips in a package, metallization, thermal cycling, and parasitics in the interconnect path. Dick Otte, CEO of Promex Industries, talks about how this will change chip design and manufacturing, and how those changes are likely to unfol... » read more

Silent Data Corruption
By Ed Sperling - 12 Dec, 2022 - Comments: 0

Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Variability Becoming More Problematic, More Diverse
By Karen Heyman - 12 Dec, 2022 - Comments: 0

Process variability is becoming more problematic as transistor density increases, both in planar chips and in heterogeneous advanced packages. On the basis of sheer numbers, there are many more things that can wrong. “If you have a chip with 50 billion transistors, then there are 50 places where a one-in-a-billion event can happen,” said Rob Aitken, a Synopsys fellow. And if Intel’s... » read more

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