tag: advanced packaging

Ready, Set, Go: Outrunning Moore’s Law With 3D-IC
By Tony Mastroianni - 08 Dec, 2022 - Comments: 0

By Anthony Mastroianni and Gordon Allan, Siemens EDA 3D ICs are an exciting and promising extension of heterogeneous advanced package technology into the third dimension. Although far from mainstream, 3D IC’s time is coming, as chiplet standardization efforts and supporting tool developments begin to make 3D IC practicable and profitable to more players – big and small – and products w... » read more

IC Stresses Affect Reliability At Advanced Nodes
By Ann Mutschler - 08 Dec, 2022 - Comments: 1

Thermal-induced stress is now one of the leading causes of transistor failures, and it is becoming a top focus for chipmakers as more and different kinds of chips and materials are packaged together for safety- and mission-critical applications. The causes of stress are numerous. In heterogeneous packages, it can stem from multiple components composed of different materials. “These materia... » read more

Advanced Auto-Routing For TSMC InFO Technologies
By Paul McLellan - 08 Dec, 2022 - Comments: 0

At the recent TSMC OIP Symposium, John Park presented 'Advanced Auto-Routing for TSMC InFO Technologies.' InFO stands for "integrated fanout" and is the lower performance, lower complexity technology for advanced packaging. For details of TSMC's whole packaging portfolio, see my post TSMC OIP: 3DFabric Alliance and 3Dblox. Here's the slide TSMC presented from that presentation on InFO. As you... » read more

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

The Computational Electromagnetics Simulation Challenge Of 3D-IC
By Kelly Damalou - 29 Nov, 2022 - Comments: 0

By Kelly Damalou and Matt Commens Innovation in semiconductor design today is energized primarily by AI/ML, data centers, autonomous and electric vehicles, 5G/6G, and IoT. Recently developed 2.5 and 3D-IC silicon-based packaging technologies have advanced the state of the art beyond SoC technologies which first united digital, analog, and memory functions on a single chip in the '90s. These ... » read more

An Organic Package Designer’s Guide To Transitioning To FOWLP And 2.5D Design
By Siemens EDA - 23 Nov, 2022 - Comments: 0

The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. In most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additi... » read more

Is UCIe Really Universal?
By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

Solving Thermal Coupling Issues In Complex Chips
By Ann Mutschler - 10 Nov, 2022 - Comments: 0

Rising chip and packaging complexity is causing a proportionate increase in thermal couplings, which can reduce performance, shorten the lifespan of chips, and impact overall reliability of chips and systems. Thermal coupling is essentially a junction between two devices, such as a chip and a package, or a transistor and a substrate, in which heat is transferred from one to the other. If not... » read more

Balancing Power And Heat In Advanced Chip Designs
By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

Cost Characteristics of the 2.5D Chiplet-Based SiP System
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies" was published by researchers at UCSB, University of California, Santa Barbara. Abstract: "The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via various inter-chiplet connection and heterogeneous integration. However, it is not known how to ... » read more

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