tag: AI

GenAI’s Breakneck Pace Is Reshaping The Semiconductor Industry
By Alex Burlak - 10 Jul, 2025 - Comments: 0

Humankind is witnessing a technological revolution so extreme that its full magnitude might extend beyond the scope of our intellect. Generative AI (GenAI) is doubling its performance every six months [1], outpacing Moore's law in what the industry calls Hyper Moore's Law. Some cloud AI chipmakers expect to double or triple performance every year for the next ten years [2]. In this three-part b... » read more

The Data Dilemma In Semiconductor Testing And Why It Matters: Part 2
By Roberto Colecchia - 10 Jul, 2025 - Comments: 0

In Part 1, we explored the challenges of implementing machine learning and real-time analytics in semiconductor testing—chiefly, the difficulty of transferring device test data across multiple locations and organizations. In this post, we introduce Data Feed Forward (DFF) as it applies to ACS Advantest. What is ACS DFF? ACS DFF is a cloud-enabled solution designed to simplify, secure... » read more

EDA Startups At DAC 2025
By Jesse Allen - 09 Jul, 2025 - Comments: 0

The 62nd DAC showcased numerous new exhibitors in 2025, including tool and IP providers, design services firms, and component marketplaces. New EDA startups, in particular, had a robust showing, with entrepreneurial engineers seeking to tackle the increasingly complex challenges facing modern chip design with fresh approaches. AI was a strong theme throughout the show, with companies of all ... » read more

Shrinking LLMs With Self-Compression
By Jakub Przybyl - 08 Jul, 2025 - Comments: 0

Language models are becoming ever larger, making on-device inference slow and energy-intensive. A direct and surprisingly effective remedy is to prune complete channels whose contribution to the task is negligible. Our earlier work introduced a training-time procedure – Self-Compression [1, 4] – that lets back-propagation decide the bit-width of every channel, so unhelpful ones fade away. T... » read more

AI: A New Tool For Hackers, And For Preventing Attacks
By Ann Mutschler - 08 Jul, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss hardware security challenges, including new threat models from AI-based attacks, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit Arora, seni... » read more

The Complete Guide To Intelligent Edge Technology
By Neeta Shenoy - 08 Jul, 2025 - Comments: 0

The rise of edge technology is transforming how data is processed and decisions are made, right where data is generated. Unlike traditional cloud computing, intelligent edge computing pushes processing closer to the source, enabling faster responses and improved efficiency. The global edge AI market reflects this shift, which was valued at $20.78 billion in 2024. By 2030, it's projected to gro... » read more

Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
By Nilesh Kamdar - 02 Jul, 2025 - Comments: 2

After 26 years in the electronics industry, I've witnessed countless technological shifts, but few have been as transformative — or as promising — as what we're experiencing with the CHIPS Act. I spoke at a recent 62nd DAC panel discussion alongside industry colleagues Saverio Fazzari from Booz Allen Hamilton and Vivek Prasad from a non-profit organization established to operate the Nationa... » read more

Novel Assembly Approaches For 3D Device Stacks
By Laura Peters - 30 Jun, 2025 - Comments: 0

The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved but the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

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