What Transistors Will Look Like At 5nm


Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node. But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. The... » read more

Blog Review: Aug. 10


Is the end near for FinFETs? Applied's Mike Chudzik digs into the impact of rising parasitic resistance and parasitic capacitance and the challenges of scaling to 5nm. Cadence's Paul McLellan checks out the method UC Berkeley is using to build RISC-V processors. Mentor's Colin Walls warns that in C even the simplest things, like the declaration of variables, have pitfalls for the unwary. ... » read more

The Week In Review: Manufacturing


Fab tools Lam Research’s proposed move to acquire KLA-Tencor has been pushed out for the second time. The deal was supposed to be completed by mid-2016. Then, it was pushed out to the third quarter amid regulatory issues. Now, the companies hope to close the deal by the fourth quarter of 2016. “The KLA-Tencor acquisition is expected to close in the December quarter. This reflects another p... » read more

Material And Process Challenges In A Changing Memory Landscape


Moore’s Law has fueled the semiconductor industry’s growth for decades. But as the complexity of scaling increases, extending the economics of Moore’s Law is becoming a challenge. One example illustrating the challenges of maintaining the economic benefits of Moore’s Law is the difficulty of IC chip patterning. Today, this requires an expensive litho scanner, a complicated spacer and... » read more

200mm Equipment Shortfall


A surge in demand for consumer electronics, communications ICs, sensors and other products has created a shortage in 200mm fab capacity that shows no signs of abating. None of these chips need to be manufactured using the most advanced processes, and there have been enough tweaks to processes at established nodes to eke even more out of existing processes. But that has left chipmakers strugg... » read more

Blog Review: July 20


Applied's Er-Xuan Ping addresses the challenges facing materials and processing in a changing memory landscape, and the opportunities that may arise. Cadence's Paul McLellan looks at teaching neural networks to perceive things more like humans do, through German traffic signs. Mentor's Colin Walls digs into managing timing and peripherals in embedded systems. Synopsys' Robert Vamosi ch... » read more

The Week In Review: Manufacturing


Fab and test equipment The wafer inspection market is heating up. For example, Applied Materials announced its new e-beam inspection system for use in foundry, logic, DRAM and 3D NAND applications. In addition, KLA-Tencor introduced six wafer defect inspection and review systems for leading-edge IC device manufacturing. National Instruments has rolled out a second-generation vector sig... » read more

E-beam Vs. Optical Inspection


The wafer inspection business is heating up as chipmakers encounter new and tiny killer defects in advanced devices. Last month ASML Holding entered into an agreement to acquire Hermes Microvision (HMI), the world’s largest e-beam inspection vendor, for $3.1 billion. The proposed move propelled ASML into the e-beam wafer inspection market. In addition, [getentity id="22817" e_name="Appl... » read more

Blog Review: July 6


Cadence's Chris Rowen discusses optimizing neural networks for low-energy and high-throughput applications in his latest video. What should you include in an IoT chip? Synopsys' Eric Huang presents the case for building in USB. Mentor's Matthew Hogan takes a look at what's needed for speedy interconnect robustness verification. Rambus' Aharon Etengoff digs into a potential new enterpri... » read more

The Week In Review: Manufacturing


Fab tools Applied Materials has officially rolled out the Producer Selectra system, a selective etch tool. The system falls under the loosely defined category called atomic layer etch (ALE). Applied’s technology addresses a number of challenges. Today’s advanced chips have complex structures. They may also have deep and narrow trenches. One of the challenges is the inability of wet ... » read more

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