tag: Cadence

Chiplets For The Masses
By Brian Bailey - 03 Mar, 2021 - Comments: 2

Chiplets are a compelling technology, but so far they are available only to a select few players in the industry. That's changing, and the industry has taken little steps to get there, but timing for when you will be able to buy a chiplet to integrate into your system remains uncertain. While new fabrication nodes continue to be developed, scaling is coming to an end, be it for physical or e... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Feb, 2021 - Comments: 0

Cadence completed the acquisition of NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine. Founded in 1993 as a spin-off of the Vrije Universiteit Brussel (VUB), NUMECA was based in Brussels, Belgium. Terms of the deal were not disclosed... » read more

Firmware Skills Shortage
By Brian Bailey - 25 Feb, 2021 - Comments: 0

Good hardware without good software is a waste of silicon, but with so many new processors and accelerator architectures being created, and so many new skills required, companies are finding it hard to hire enough engineers with low-level software expertise to satisfy the demand. Writing compilers, mappers and optimization software does not have the same level of pizazz as developing new AI ... » read more

Hyperscaling Cyber-Physical Systems
By Frank Schirrmeister - 25 Feb, 2021 - Comments: 0

As consumers, we are not always aware of all the data created around us by our cars, mobile devices, computers, and day-to-day consumer products. In most cases, we are even less aware of what's going on during the development and production of today's devices and systems that we have gotten so used to. During the most recent DATE 2021 conference, the special day on cyber-physical systems gave s... » read more

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

Big Challenges In Verifying Cyber-Physical Systems
By Ed Sperling - 25 Feb, 2021 - Comments: 0

Semiconductor Engineering sat down to discuss cyber-physical systems and how to verify them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architect specialist at STMicroelectronics. This discussion was... » read more

5G NR Design For eMBB
By Cadence - 24 Feb, 2021 - Comments: 0

This white paper examines the design challenges for eMBB products and provides examples of how these challenges can be overcome using the co-design capabilities in Cadence AWR Design Environment software. Click here to download with registration. » read more

Blog Review: Feb. 24
By Jesse Allen - 24 Feb, 2021 - Comments: 0

Siemens EDA's Harry Foster checks out the efficiency and effectiveness of verification on ASIC and IC designs with a look at how many projects meet the original schedule, the number of required spins, and classification of functional bugs. Cadence's Paul McLellan listens in as Philippe Magarshack of ST Microelectronics on how the company uses massive amounts of data generated by its fabs to ... » read more

Blog Review: Feb. 17
By Jesse Allen - 17 Feb, 2021 - Comments: 0

In a video, Synopsys' Tim Mackey warns that IoT device manufacturers are dealing with a serious challenge when it comes to security and points to the types of software threats that could impact IoT products. Siemens' Paul van Straten finds that the rise in vehicle complexity and intensified global competition means traditional automotive OEMs will need to explore new approaches to vehicle de... » read more

Design For Reliability
By Brian Bailey - 15 Feb, 2021 - Comments: 1

Circuit aging is emerging as a mandatory design concern across a swath of end markets, particularly in markets where advanced-node chips are expected to last for more than a few years. Some chipmakers view this as a competitive opportunity, but others are unsure we fully understand how those devices will age. Aging is the latest in a long list of issues being pushed further left in the desig... » read more

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