tag: Cadence

Speeding Up Mask Production
By Mark LaPedus - 12 Sep, 2016 - Comments: 0

Chip production is becoming more complex and expensive at each node. As a result, chipmakers require a growing number of new manufacturing technologies to enable the next wave of devices at advanced nodes. In the fab, for example, the most obvious need is extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. In addition, chipmakers also need a new class of atomic-level proces... » read more

Controlling Heat
By Ann Mutschler - 12 Sep, 2016 - Comments: 0

Modeling on-chip thermal characteristics and chip-package interactions is becoming much more critical for advanced designs, but how to get there isn't always clear. Every chip, based on its target application, has a thermal design power (TDP) target. This is the typical power it can consume without overreaching the acceptable thermal limits in its intended environment. But in order to rate t... » read more

GlobalFoundries Rolls Out 12nm FD-SOI Process
By Jeff Dorsch - 08 Sep, 2016 - Comments: 0

GlobalFoundries uncorked its 12FDX platform, incorporating a 12nm fully-depleted silicon-on-insulator process technology. The foundry’s Fab 1 in Dresden, Germany, will support customer development with the 12nm process, with product tape-outs scheduled for the first six months of 2019. The 12FDX technology follows the company’s 22FDX platform involving a 22-nanometer process. The foundr... » read more

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

Managing Power Without Impacting Design Intent
By Christine Young - 08 Sep, 2016 - Comments: 0

The good news is that there are many techniques available to optimize power in your design. The not-so-good news? Many of these power management techniques also create new complexities in the physical and functional behavior of electronic designs. Fortunately, there’s more good news: implementing a power-aware verification methodology can help you verify power optimization without detracti... » read more

Power Options And Issues
By Ann Mutschler - 08 Sep, 2016 - Comments: 0

In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Integration IP Helps IP Integration
By Brian Bailey - 08 Sep, 2016 - Comments: 0

You might not know much about the MIPI Alliance if you aren't designing mobile phones, but you will soon. Other application areas are taking interest in what this group has accomplished. The alliance was founded in 2003 to create standards for hardware and software interfaces in mobile devices. Successful examples include a camera serial interface (CSI) and a display serial interface (DSI), ... » read more

Blog Review: Sept. 7
By Jesse Allen - 07 Sep, 2016 - Comments: 0

In a video, Cadence's Kishore Kasamsetty contends that one-size-fits-all DDR PHY no longer works and looks into the unique requirements of different application segments. Synopsys' Eric Huang gives a brief overview of the five components required for USB certification. Mentor's Andrew Macleod presents a way Apple Cars could rake in revenue beyond the vehicle itself. When it comes to hi... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Auto Security And Technology Questions Persist
By Ann Mutschler - 01 Sep, 2016 - Comments: 1

While carmakers continue to add increasingly sophisticated driver assist features to new models, semiconductor industry ecosystem players are ramping up their foundation knowledge of what is needed from a technology and security perspective. Fortunately, it appears many existing semiconductor design tools will fit the bill as part of new approaches for automotive design. Mike Stellfox... » read more

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