tag: Cadence

Rethinking Verification For Cars
By Ann Mutschler - 29 Sep, 2016 - Comments: 0

As the amount of electronic content in a car increases, so does the number of questions about how to improve reliability of those systems. Unlike an [getkc id="76" kc_name="IoT"] device, which is expected last a couple of years, automotive electronics fall into a class of safety-critical devices. There are standards for verifying these devices, new test methodologies, and there is far mo... » read more

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

How High-Level Synthesis Was Used To Develop An Image-Processing IP Design From C++ Source Code
By Cadence - 28 Sep, 2016 - Comments: 0

Imagine working long and hard on a design, only to learn that you need to add new (and more complex) functionality a few months before your targeted tapeout. How can you deliver the performance and capabilities expected in the same timeframe? For Bosch, high-level synthesis (HLS) provided the solution. In this paper, we will discuss how HLS technology enabled the team to meet an aggressive sche... » read more

Blog Review: Sept. 28
By Jesse Allen - 28 Sep, 2016 - Comments: 0

Cadence's Paul McLellan provides a glimpse of TSMC's roadmap, including what to look for at 7nm, low-power processes, and the ecosystem around the process. Mentor's Stephen Pateras notes that throughout the evolution of DFT, two rules for success have persisted. Early analysis suggests the largest DDoS attack in history, targeted at security reporter Brian Krebs, may have leveraged flaws ... » read more

The Week In Review: Design
By Jesse Allen - 23 Sep, 2016 - Comments: 0

Tools Real Intent updated its Ascent Lint product, adding 50 new customer-driven rules, improved support of VHDL and System Verilog, and a new database-driven debugger with an integrated source browser and improved schematic visualization. IP ARM launched a new real-time processor with advanced safety features for autonomous vehicles and medical and industrial robots. The processor, Co... » read more

Blog Review: Sept. 21
By Jesse Allen - 21 Sep, 2016 - Comments: 0

Mentor's Ricardo Anguiano takes a look at a proposal to prevent auto accidents from becoming pile-ups: the relaying of hazard information to the cloud and on to upcoming vehicles. Why get rid of 3.5mm audio jacks? Synopsys' Michael Posner says it's all about the power optimization in the upcoming USB Type-C digital audio specification. NXP's Anand Kannan also thinks Type-C should be the d... » read more

Plugging Holes In Machine Learning
By Ed Sperling - 19 Sep, 2016 - Comments: 0

The number of companies using machine learning is accelerating, but so far there are no tools to validate, verify and debug these systems. That presents a problem for the chipmakers and systems companies that increasingly rely on machine learning to optimize their technology because, at least for now, it creates the potential for errors that are extremely difficult to trace and fix. At the s... » read more

The Week In Review: Design
By Jesse Allen - 16 Sep, 2016 - Comments: 0

IP Sonics unveiled Energy Processing Unit (EPU) IP, based on the company's ICE-Grain power architecture, to better manage and control circuit idle time. The IP facilitates design of SoC power architecture and implementation and verification of the resulting power management subsystem. Synopsys debuted ARC SEM security processors with timing and power randomization features to protect agai... » read more

Blog Review: Sept. 14
By Jesse Allen - 14 Sep, 2016 - Comments: 0

Are wide bandgap lll-V power devices feasible? Applied's Ben Lee considers the challenges, and potential rewards, of silicon carbide and gallium nitride. DVCon India chair Gaurav Jalan chats with keynote speaker Alok Jain about the challenges of verifying complex SoCs, the unique verification needs of the IoT, and what might lie beyond UVM. From power intent abstraction to automatic power... » read more

Cars, Security, and HW/SW Co-Design
By Jeff Dorsch - 13 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy