tag: Cadence

Electronics Butterfly Effect
By Brian Bailey - 27 Aug, 2015 - Comments: 1

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Why Implementation Matters To System Design And Software
By Frank Schirrmeister - 27 Aug, 2015 - Comments: 0

There has been quite some discussion in the recent past how well abstraction really works in enabling system design and verification. As I admitted in “Confessions of an ESL-Aholic” a while back, I have revised my view significantly over the years. While thinking originally of abstraction more as an panacea, it turns out that important decisions and analyses, such as for power and performan... » read more

What Happened To ESL
By Ann Mutschler - 27 Aug, 2015 - Comments: 3

Electronic system level ([getkc id="48" kc_name="ESL"]) is a design methodology idea that gained steam in the last 20 years centered mainly around the idea of using higher levels of abstraction to define and implement an electronic design. It was defined and promoted by industry analyst Gary Smith, then at Gartner-Dataquest, and so much has been written on this topic over the years that ESL ... » read more

Gate-Level Simulation Methodology
By Cadence - 26 Aug, 2015 - Comments: 0

The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of gate-level simulation (GLS) applications including design for test (DFT) and low- power considerations. As a result, in order to complete the verification requirements on time, it becomes extr... » read more

Blog Review: Aug. 26
By Jesse Allen - 26 Aug, 2015 - Comments: 0

Synopsys' Marc Greenberg attended IDF and learned more about the newly announced Intel/Micron 3D XPoint memory technology named Optane including initial ship dates and some implementation details. In concluding his analysis of the 2014 Functional Verification Study, Mentor's Harry Foster reveals an unexpected finding about design size and respins. How do you keep your power grid from bein... » read more

Blog Review: Aug. 19
By Jesse Allen - 19 Aug, 2015 - Comments: 1

Several of this week's top reads from Ansys' Justin Nescott sound like they're straight from the pages of sci-fi novels (and comic books). An MIT project is getting close to creating the Iron Man suit, one company plans to finally build a space elevator, and Los Angeles takes an innovative approach to fighting the California drought: 96 million black plastic balls. Smartphones are so yestery... » read more

Fundamental Shifts In Chip Business
By Ed Sperling - 17 Aug, 2015 - Comments: 3

Shifting business models, acquisitions, minority investments and increasing uncertainty are creating fundamental shifts in the semiconductor industry that could redefine who is successful in which markets for years to come. The announcement today that [getentity id="22671" e_name="Rambus"] is developing memory controller chips, expanding its business beyond just creating IP for the memory an... » read more

How Much Security Is Enough?
By Ed Sperling - 17 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the current state of [getkc id="223" kc_name="security"] and what must be done in the future, with Denis Noël, head of cyber security solutions at [getentity id="22499" e_name="NXP"]; Serge Leef, vice president of new ventures at [getentity id="22017" e_name="Mentor Graphics"]; Andreas Kuehlman, senior vice president and general manager of the soft... » read more

Thermal Issues Getting Worse
By Ann Mutschler - 14 Aug, 2015 - Comments: 2

Making sure that smartphone you’re holding doesn’t burn your face when you make a call requires a tremendous amount of engineering effort at all levels of the design - the case, the chips, the packaging. The developers of the IP subsystems in that smartphone must adhere to very strict power and energy thresholds so the OEM putting it all together can stick to some semblance of a product des... » read more

DVFS On The Sidelines
By Brian Bailey - 13 Aug, 2015 - Comments: 2

Power reduction is one of the most important aspects of chip design these days, but not all power reduction techniques are used equally. Some that were once important are fading and dynamic voltage, and frequency scaling (DVFS) is one of them. What's changed, and will we see a resurgence in the future? What is it? DVFS has physics powerfully in its favor. As Vinod Viswanath, director of res... » read more

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