tag: Cadence

Stacked Die, Phase Two
By Ed Sperling - 09 Apr, 2015 - Comments: 0

The initial hype phase of [getkc id="82" kc_name="2.5D"] appears to be over. There are multiple offerings in development or on the market already from Xilinx, Altera, Cisco, Huawei, IBM, AMD, all focused on better throughput over shorter distances with better yield and lower power. Even Intel has jumped on the bandwagon, saying that 2.5D will be essential for extending [getkc id="74" comment="M... » read more

The Wild West Of Automotive
By Brian Bailey - 09 Apr, 2015 - Comments: 0

Automotive is considered one of the great new markets for EDA and IP. Electronic complexity is increasing rapidly, product update cycles are decreasing, and new standards mean that many of the old ways of doing development are no longer possible. Such change creates opportunity, along with a certain degreed of confusion. As the number of discrete systems increases, so do costs. Electronics c... » read more

UPF 3.0 Moves Toward Ratification
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

[gettech id="31044" t_name="UPF"] (Unified Power Format) 3.0 — the fourth incarnation in 10 years — is moving closer to the IEEE ballot process. Erich Marschner, verification architect at [getentity id="22017" e_name="Mentor Graphics"] and vice chair of the [gettech id="31043" comment="IEEE 1801"] working group, explained the working group is as close as possible to being on schedule for... » read more

How We’ll Get There from Here
By Brian Fuller - 09 Apr, 2015 - Comments: 0

The electronics industry is like a battleship with remarkable handling properties. I thought about it this week sitting at an industry event a day after stumbling across Neptune—the technology project, not the god. Those two experiences forced me to rethink some fundamental assumptions about system design and how the ecosystem responds to change. If you’ve not heard of Neptune, it�... » read more

Is Dark Silicon Wasted Silicon?
By Ann Mutschler - 09 Apr, 2015 - Comments: 0

The concept of dark silicon sounds almost mysterious, but it is a simple matter of physics. With advances in technology nodes and the ability to pack more and more transistors on the same die, design engineers are reaching a wall where only a fraction of a design can be powered on due to power and thermal implications. Moreover, the challenges that force this kind of complex power managemen... » read more

Does Fast Simulation Help Debug Productivity?
By Brian Bailey - 09 Apr, 2015 - Comments: 0

It is nice when a reporter manages to get the scoop of the century, and that was the case at a lunch panel hosted by [getentity id="22032" e_name="Cadence"] at the recent Design and Verification Conference (DVCon) in Santa Clara, CA. Brian Bailey, technology editor for Semiconductor Engineer was the moderator for the panel and broke the news to the crowd. Cadence had developed a logic [getkc id... » read more

Blog Review: April 8
By Jesse Allen - 08 Apr, 2015 - Comments: 0

No other human endeavor has seen such sustained exponential growth. But it's the end of an era for Moore's Law, says Cadence's Axel Scherer—and only the beginning of one for Moore's Law 2.0. Synopsys' Amit Sharma tackles the cache coherency extensions of the ARM Advanced eXtensible Interface (AXI) and points out that the infrastructure required for their verification needs to scale up in s... » read more

Week 43: Get Ready For A Sizzling DAC Pavilion
By Anne Cirkel - 03 Apr, 2015 - Comments: 0

We are having some fantastic spring weather here in Oregon. Check out the little video clip of my crazy dog Diesel at the Oregon Coast shot a few weeks back. Mind you, there is no ball in that chucker he’s dancing around for. That’s because, Kismet, my other dog you can see in the foreground, caught the ball and is bringing it to me, occasionally looking back over her shoulder at her somewh... » read more

The Week In Review: Design/IoT
By Jesse Allen - 03 Apr, 2015 - Comments: 0

IP Synopsys unveiled a line of vision processor IP cores optimized for high-performance embedded vision applications. The processors can be used with any host processors, sport multiple cores and implement a convolutional neural network to deliver more than 1000 GOPS/W, plus a software programming environment that supports OpenVX and OpenCV libraries. Deals Andes Technology and eMemory Tec... » read more

Will Wearables Work Well Enough?
By Ed Sperling - 02 Apr, 2015 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler The rollout of the Apple Watch later this month has reset expectations for the wearable electronics market, just as early implementations of the Pebble, Fitbit and Google Glass helped raise awareness about a new level of portability and connectivity. Early projections are for strong sales, which in turn will propel a new level of connectedness for the ... » read more

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