tag: Cadence

First Time Success and Cost Control
By Brian Bailey - 01 Apr, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

Blog Review: April 1
By Jesse Allen - 01 Apr, 2015 - Comments: 0

A Russian plan to build a massive cargo plane to deliver tanks at supersonic speed—A roll of tape coated in squid proteins provides perfect camouflage—A yacht made of volcanic fibers battling the world's roughest seas: Ansys' Justin Nescott finds everything for a James Bond movie in this week's top tech articles. Writing for Synopsys, Broadcom's Hari Balisetty looks at reusable sequences... » read more

Architecturally Optimizing Memory Bandwidth
By Ann Mutschler - 27 Mar, 2015 - Comments: 0

Making sure that an SoC’s [getkc id="22" kc_name="memory"] bandwidth is optimized is a crucial part of the design process today given its significance toward overall system performance. There are many ways to approach this issue, and all of them can have a direct bearing on the competitiveness of a chip in terms of both power and performance. So where should you start? “Number one, c... » read more

What Is Functional Accuracy?
By Ann Mutschler - 26 Mar, 2015 - Comments: 0

What it means to be functionally accurate in the context of [getkc id="104" kc_name="virtual platforms"] varies greatly, depending upon whom you ask and even when you ask them. But that doesn’t mean that functional accuracy isn’t useful. Jon McDonald, technical marketing engineer for the design and creation business at [getentity id="22017" e_name="Mentor Graphics"], expects to see a lot... » read more

System Design Enabling The Human Intranet
By Frank Schirrmeister - 26 Mar, 2015 - Comments: 0

Against the always-impressive backdrop of the French Alps, DATE took place earlier this month in Grenoble. DATE has quietly transformed from a European version of DAC into a very interesting technical conference with some very high-caliber attendees. This year, I had the pleasure to participate as session chair for the design tools section, themed “Designing Electronics for the Internet of Th... » read more

Blog Review: March 25
By Jesse Allen - 25 Mar, 2015 - Comments: 0

From brain implants that recover memories to color-shifting shoes, Ansys' Bill Vandermark features sci-fi visions of the future that are becoming reality in his top five tech picks of the week. In the world of embedded software, is a black box better? Mentor's Colin Walls questions whether the advantages that come of having full access to source code outweigh the downsides. Cadence's Neel... » read more

The Week In Review: Design/IoT
By Jesse Allen - 20 Mar, 2015 - Comments: 0

Mergers & Acquisitions Silvaco acquired Invarian, anticipating integration of Invarian's methodology will accelerate adoption of concurrent power-voltage-thermal analysis. Legal A U.S. District Court judge ordered Kilopass to pay $5.5 million to Sidense for legal fees incurred in Kilopass' patent infringement suit against Sidense. That lawsuit was  dismissed in 2012. Sidense filed... » read more

3D Effects At 20nm And Beyond
By Ann Mutschler - 19 Mar, 2015 - Comments: 0

At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Blog Review: March 18
By Jesse Allen - 18 Mar, 2015 - Comments: 0

How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

First Time Success And Cost Control
By Brian Bailey - 13 Mar, 2015 - Comments: 0

First time success has been the ultimate goal for semiconductor companies due to escalating mask costs, as well as a guiding objective for the development of EDA tools, especially in the systems and verification space. These pressures are magnified for the [getkc id="76" comment="Internet of Things"] (IoT), especially the edge devices. Have system-level tools been able to contribute to first ti... » read more

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