tag: Cadence

Next Bonanza: Security Holes
By Ed Sperling - 07 Jul, 2014 - Comments: 0

Security threats—both real and potential—are beginning to reshape the semiconductor business. These threats are drawing venture capitalists back into the industry as they race for the next big opportunity. They are blurring the lines between software and hardware, as threats grow in complexity at every level of a device and its myriad and sometimes perpetual connections to the outside wo... » read more

DFM And Multipatterning
By Ed Sperling - 03 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss DFM at advanced nodes with Kuang-Kuo Lin, director of foundry design enablement at Samsung Electronics; Jongwook Kye, lithography modeling and architecture fellow at GlobalFoundries; David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics; Ya-Chieh Lai, engineering director for DFM/CLS silicon signoff and ver... » read more

The Week In Review: Design
By Ed Sperling - 03 Jul, 2014 - Comments: 0

Tools The Android Open Source Project for ARM’s v8-A architecture is now available as part of the Linaro 14.06 release. The release has been tested on 64-bit multicore processors. Research NXP conducted a secure credit card survey that showed Americans are more likely to pay cash following security breaches at large retail chains, with 69% in favor of secure credit cards to guard against... » read more

Blog Review: July 2
By Ed Sperling - 02 Jul, 2014 - Comments: 0

Mentor’s Nazita Saye has reservations about driverless cars. Sometimes it’s actually fun to drive—and sometimes it isn’t. Cadence’s Brian Fuller is a bit more optimistic about driverless cars. He says that from the standpoint of safety, efficiency and environment, autonomous vehicles will be a big step forward—if and when some critical problems are solved. And along the same... » read more

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

Everyone Is A Programmer
By Ed Sperling - 26 Jun, 2014 - Comments: 0

There was a time when so many people didn’t know how to program their VCRs that OEMs stopped adding clocks because it was embarrassing to have them constantly blinking “12:00.” We’ve come a long way since VCRs. And that means all of us. While engineers have always enjoyed tinkering with technology, what’s changed is that everyone tinkers with technology now. Everyone programs phone... » read more

Moore’s Law Tail No Longer Wagging The Dog
By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Asynchronous Is Mostly Academic
By Ann Mutschler - 26 Jun, 2014 - Comments: 4

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and asynchronous logic. Asynchronous logic promises a number of benefits in some specific application areas, and one that buoys to the surface for potential near-term use is in the area of security a... » read more

Can EDA Keep Growing?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Slower progress at the leading edge of process technology, coupled with rising costs and fewer design starts, are changing the economics of the EDA world. Not surprisingly, there is almost a direct correlation between the shrinking number of startups in the field and the number of customers working on the most advanced nodes. So what exactly does this mean for the EDA world? Big changes, for... » read more

3 Challenges Of Delivering Configurable Semiconductor IP
By Kurt Shuler - 26 Jun, 2014 - Comments: 0

Over time, commercial IP products have morphed from single function blocks to 100% configurable IPs where no two instances are the same. In this article I point out the challenges of creating configurable IP, and the best-known practices to address them. IP Configurability Spectrum Throughout the history of chip design, there has been a spectrum of configurability that has been built into i... » read more

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