tag: Cadence

Game Of Eco Systems
By Frank Schirrmeister - 26 Jun, 2014 - Comments: 0

My first ever blog post on May 28, 2008, was called “May you live in interesting times …”, starting with “the view from the top” at Synopsys. At the time, my focus was abstraction levels and how the industry has been moving upwards for decades. While it is not a Chinese proverb after all (read my blog above), we still do live in interesting times, perhaps more so that ever. One of the... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Blog Review: June 25
By Ed Sperling - 25 Jun, 2014 - Comments: 0

Is the Amazon Fire smart phone a paradigm shift? Cadence’s Brian Fuller looks at the first application-specific smart phone and why it’s noteworthy—regardless of how well it fares against phones made by Apple and Samsung. Rambus’ Deepak Chandra Sekar digs deep into interconnect technology and where the prevailing winds are blowing—copper barrier/cap/liner optimization, a slowdown i... » read more

The Week In Review: Design
By Ed Sperling - 20 Jun, 2014 - Comments: 0

M&A Cadence completed its acquisition of Jasper Design Automation, using cash and revolving credit to finance the deal. It will explain the impact on 2014 financial results in fiscal 2015. Jasper’s team, led by CEO Kathryn Kranen, will now report to Cadence senior VP Charlie Huang in Cadence’s System & Verification Group. The deal was first announced in April. Tools Coverity un... » read more

Five Disruptive Test Technologies
By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

Ethernet: The Highway For Automotive Electronics?
By Joanne Itow - 19 Jun, 2014 - Comments: 0

What happens when technology from the fast paced communication industry makes a move into the traditional automotive industry? Semiconductor marketers and even the automotive industry are talking about revolutionary changes inside and outside the vehicle. What kinds of changes? Ethernet and sensors. There’s a lot of excitement and enthusiasm over the prospect of cars with Ethernet networki... » read more

Blog Review: June 18
By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

New Uses For Emulation
By Ed Sperling - 16 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

Do SoCs Need Earthquake Insurance?
By Ann Mutschler - 13 Jun, 2014 - Comments: 1

RTL sign-off is not a new term, but with SoCs that can be comprised of up to 90% IP blocks combined with the complexities that advanced manufacturing process nodes bring, RTL sign-off activities become a process that demands a more comprehensive approach. “There is a fundamental shift going on in chip design in general in that there is a bigger focus on so-called system on chip (SoC) desig... » read more

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