tag: Cadence

S-L Power Modeling Gains Steam
By Ann Mutschler - 12 Jun, 2014 - Comments: 1

Power analysis, architectural exploration and optimization of an SoC is a hot topic of discussion today. It is well accepted this must be addressed at a higher level of abstraction because not just the hardware must be taken into account with power intent and power management structures. It has to be viewed from a system point of view, as well, where the hardware resides along with the opera... » read more

Computer Vision’s Enormous Challenges Ahead
By Brian Fuller - 12 Jun, 2014 - Comments: 0

SAN FRANCISCO — There is a constant, humming tension between what Moore's Law delivers and what consumers expect from electronics systems design. We're on the verge of seeing this in the coming decade in computer vision, an application that has enormous potential to transform society. In the meantime, enormous challenges and decisions lie ahead on the road to transformation. Embedded Vi... » read more

What’s Wrong With Power Signoff
By Ed Sperling - 12 Jun, 2014 - Comments: 0

Reducing power has emerged as the most pressing issue in the history of technology. On one hand, it’s the biggest opportunity the electronics industry has ever seen. On the other, the abuse of cheap power has been linked to global warming, human catastrophe, and geopolitical strife. In all cases, the semiconductor increasingly finds itself at the vortex of all of this, and making chips more e... » read more

Blog Review: June 11
By Ed Sperling - 11 Jun, 2014 - Comments: 0

eSilicon’s Jack Harding says that EDA and semiconductors need to focus heavily on recruiting the next generation of brilliant engineers. This technology is cool, and even better it makes all the other cool technology work. It’s time to remind the rest of the world. Cadence’s Brian Fuller distills a panel discussion at DAC on computer vision—the sensors that enable driverless cars, a... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Blog Review: June 4
By Ed Sperling - 04 Jun, 2014 - Comments: 0

Sonics' Drew Wingard looks at the challenges of IP integration, from standards to re-use to the need for intelligence on the network. Given the focus on IP integration, as well as the myriad challenges, this is very timely information. ARM's Karthik Ranjan has an interesting theory about why Java developers wear glasses. Ansys' Justin Nescott unearths the five most interesting engineering... » read more

Executive Insight: Simon Segars
By Ed Sperling - 03 Jun, 2014 - Comments: 0

SE: What concerns you most? Segars: In the context of design and where chip design is going, ARM is a long-term business. We’re doing stuff now that is going to ship in five years’ time. Obviously, for everyone in this space, Moore’s Law has been a fantastic thing. It’s enabled us to achieve really fantastic scaling of transistors, and everyone knows that is getting harder and harder... » read more

The Week In Review: Design
By Ann Mutschler - 30 May, 2014 - Comments: 0

M&A ARM said it is acquiring Duolog Technologies, a player in design configuration and integration technology for the semiconductor industry. ARM said this will expand its position for deploying complex system IP including debug and trace IP. Terms of the deal have not been disclosed. Tools and IP ARM’s Cortex A9 core is at the heart of a new secure processor from Broadcom aimed at endpo... » read more

New Uses For Emulation
By Ed Sperling - 29 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

Easing The Path To Evolution
By Ann Mutschler - 29 May, 2014 - Comments: 1

On the surface, revolutionary changes in EDA seem unlikely due to the risk of replacing costly tools, flows and methodologies. But are they really? The answer depends on whom you ask. For Part One, click here. Risk is a big part of the equation here. “There are always pioneers in an organization and what you need to do is find someone who is willing to take some risk and typically it’s o... » read more

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