tag: Cadence

Blog Review: May 28
By Ed Sperling - 28 May, 2014 - Comments: 0

Ansys’ Robert Harwood examines the crossover between drones and 3D printing—particularly ones that can make repairs in inaccessible or hazardous areas. That could make both of them more popular. Mentor’s Mathew Clark puts a new spin on the term “gumming up the works.” Poor little things. Cadence’s Brian Fuller drills into Google’s Project Ara, the magnetic LEGO architecture ... » read more

The Week In Review: Design
By Ed Sperling - 23 May, 2014 - Comments: 0

M&A Mentor Graphics acquired Nimbic, which makes simulation software for power and signal integrity and electromagnetic interference. No purchase price was given. Synopsys’ Coverity subsidiary acquired Kalistick, which makes cloud-based software solutions to boost test efficiency. Terms of the deal were not provided. Tools and IP Sonics introduced a new development environment for... » read more

EDA Economics Changing
By Ed Sperling - 22 May, 2014 - Comments: 0

From most perspectives, there has never been a better time to be in the EDA business. Automation tools are in demand as complexity rises, and new companies jumping into the semiconductor business are starting out with commercially available tools rather than developing their own—and taking years, sometimes even decades, to replace them. EDA’s slice of the semiconductor market consistent... » read more

The Assertion Conundrum
By Ann Mutschler - 22 May, 2014 - Comments: 2

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

New Uses For Emulation
By Ed Sperling - 22 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

When And Where To Use Virtual Prototypes
By Ann Mutschler - 22 May, 2014 - Comments: 0

Just because something is technically possible doesn’t always mean it should be done. This definitely holds true currently when it comes to virtual prototypes, which have gotten a lot of attention for their potential in the SoC design process—especially for concurrent software development. While no one is pointing fingers, there are situations in which design teams have thrown themselves... » read more

Confessions Of An ESL-Aholic
By Frank Schirrmeister - 22 May, 2014 - Comments: 0

At DAC 1997 – 17 years ago – Gary Smith coined the term “Electronic System-Level” (ESL) design. Around the same time I entered EDA when becoming part of Cadence and became very involved in ESL. Things have changed over the last 17 years quite a bit. While some of the predictions did not come true, others definitely did. Over the last couple of years the tools to be counted as part of sy... » read more

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

Blog Review: May 21
By Ed Sperling - 21 May, 2014 - Comments: 0

Mentor’s Colin Walls offers up some new insights into C++ exception handling, thanks to some input from colleague Jonathan Roelofs. This one involves minimizing overhead and reducing runtime penalties. Synopsys’ Mick Posner is back in the saddle again—literally. This is about as green as it gets. Cadence’s Arthur Marris reports back on the IEEE 802.3 Ethernet standards meeting, in... » read more

EDA Races To 7nm, Despite Litho Uncertainties
By Ann Mutschler - 16 May, 2014 - Comments: 0

It’s becoming almost painful to refer to the delay with EUV, but it certainly isn’t stopping anyone on the design side from tweaking design tools or working on test chips. Clearly, things are moving ahead to 7nm even though lithography plans aren't yet clear. Steve Carlson, group marketing director in Cadence’s Office of Chief Strategy, said with regard to EUV, “They have the power p... » read more

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