tag: Cadence

Blog Review: Feb. 26
By Ed Sperling - 26 Feb, 2014 - Comments: 0

Got enough time for verification? How about a verification conference? In preparation for DVCon, Real Intent’s Graham Bell grills a panel of experts on where design ends and verification begins. The answer: It depends. Mentor’s Dennis Brophy points to the new version of the Universal Verification Methodology as a reason to attend DVCon next week. Even if you don’t plan to attend, ther... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

Blog Review: Feb. 19
By Ed Sperling - 19 Feb, 2014 - Comments: 0

Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used. Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s ... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 14 Feb, 2014 - Comments: 4

In 2004, Intel introduced a new line of Pentium chips that ran at 3.6GHz. Fast forward to today, and the company’s i7 processors run at 3.5GHz with a Turbo Boost to 3.9GHz. There have been many improvements in the meantime. There is more cache and dramatically faster access to data stored in that cache. And there are more cores with improved coherency between them. But the big problem is p... » read more

The Week In Review: System-Level Design
By Ed Sperling - 14 Feb, 2014 - Comments: 0

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

Do Chips Really Work The First Time?
By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

Power Reduction Through Sequential Optimization
By Ann Mutschler - 13 Feb, 2014 - Comments: 1

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, fundamental tradeoffs are done and the engineering team decides how much memory the system needs, what type of processor, what performance, area, power, among other things. Some people may use ... » read more

Choosing The Right Systems Design Path
By Brian Fuller - 13 Feb, 2014 - Comments: 0

I’m a cheap bastard, usually given to self-abnegation when it comes to buying material goods for myself. But I broke down and bought a runner’s watch late last year because I wanted to change up my exercise routine to run the same distances, only faster. I quickly decided against going all in and getting a GPS watch. At this point in the arc of electronics-design technology, it’s hard ... » read more

Heat Problems Grow With FinFETs, 3D-ICs
By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

Blog Review: Feb. 12
By Ed Sperling - 12 Feb, 2014 - Comments: 0

Mentor’s Colin Walls adds his perspective to a recent survey by Jim Turley, asking which part of the embedded system development process engineers would rather not change. The choices were the chip, the OS and the tools. Any guesses as to the winner? Cadence’s Richard Goering conducts an interview based on a new branch of circular logic—the CERN supercollider where the Higgs Boson was... » read more

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