tag: Cadence

Blog Review: July 31
By Ed Sperling - 31 Jul, 2013 - Comments: 0

By Ed Sperling Wherever you turn in IC design, there’s always someone talking about future problems involving the interconnect. Cadence’s Brian Fuller puts the latest speech by North Carolina State professor Paul Franzon in historical perspective—or at least in the shadow of the last dire prediction by Intel’s Mark Bohr two decades ago. Incidentally, Bohr’s warning turned out to be r... » read more

The Week In Review: July 26
By Ed Sperling - 26 Jul, 2013 - Comments: 0

By Ed Sperling Cadence’s Q2 revenue increased 11% to $362 million compared to $326 million in the same period in 2012. On a GAAP basis, net income dropped to $9 million compared with $36 million in 2012, but that decrease was impacted by the cost of recent acquisitions and integration of companies. On a non-GAAP basis, income was $61 million compared with $53 million in Q2 2012. Dassault... » read more

New Silos Form In IC Industry
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling For the past couple of decades corporations around the globe have been focused on down silos. In fact, it has become a mantra. It’s considered essential for making established corporations even more successful, and it’s almost always at the center of turnaround plans for troubled companies. Moreover, across a full spectrum of companies, it’s regularly cited by management c... » read more

Measuring Verification Productivity
By Ann Mutschler - 25 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler In this era of mammoth SoCs that require the utmost in verification complexity, it’s not enough to have a methodology. Design and verification teams also need to measure their productivity to constantly stay ahead of the curve. The more sophisticated customers are measuring a lot of things, explained Steve Bailey, marketing director at Mentor Graphics, “and for... » read more

GPUs May Speed UP EDA Algorithms
By Ann Mutschler - 25 Jul, 2013 - Comments: 1

The sequential EDA algorithms of old cannot keep pace with increasing design complexity, which is driving the industry to look at parallelism and other computational architectures such as the graphical processing unit (GPU). A 10X or 20X speedup for gate-level simulations means that a test that runs today in a week will run in less than a day, and a test that runs today in a month will run i... » read more

Experts At The Table: Automotive Electronics
By Ann Mutschler - 25 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss the opportunities in automotive electronics with Alexandre Palus, principal SoC architect at Altera; Aveek Sarkar, VP of product engineering & support at Apache; Mladen Nizic, engineering director, mixed signal solution at Cadence; and Stephen Pateras, product marketing director, silicon test solutions at Mentor Graphics. Wh... » read more

Raising The IP Abstraction Level
By Ed Sperling - 25 Jul, 2013 - Comments: 0

By Ed Sperling An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and limitations of myriad possible choices earlier in the design process. Design teams already are under pressure to meet increasingly tighter market deadlines, and it is stressing every pa... » read more

What Really Matters: User Care-Abouts In Hardware-Assisted Verification
By Frank Schirrmeister - 24 Jul, 2013 - Comments: 0

By Frank Schirrmeister Sports analogies often work well and, most certainly, they do for electronics development. When again I ran across the VISA advertisement in which Dick Fosbury is featured with his win in the high-jump competition at the 1968 Summer Olympics, I had to smile as it reminded me of hardware-assisted verification (I know, I know…twisted, you might say). Just as Fosbury chan... » read more

Blog Review: July 24
By Ed Sperling - 24 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster unleashes part six of the Wilson Research Group functional verification study, this segment digging deeper into the time spent in verification. The numbers have surpassed time spent on the design side, which either means the front-end tools are getting better or the verification problem is becoming more difficult. Cadence’s Brian Fuller interviews I... » read more

The Week In Review: July 22
By Mark LaPedus - 22 Jul, 2013 - Comments: 0

By Mark LaPedus ASML Holding has been under pressure to bring extreme ultraviolet (EUV) lithography into mass production. EUV is still delayed. Now, in their latest roadmaps, leading-edge chipmakers are counting on ASML’s 300mm EUV scanner for insertion at the 10nm node. Yet, at the same time, ASML also is working on a 450mm version of the EUV tool. “EUV (on 300mm) is a higher priority th... » read more

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