tag: Cadence

Multisourcing Options
By Ed Sperling - 27 Jun, 2011 - Comments: 0

Semiconductor Manufacturing & Design discusses the ability to move chip designs from one foundry to another with Walter Ng of Global Foundries, Michael Buehler-Garcia of Mentor Graphics, John Murphy of Cadence and Ling Hong of Kilopass. [youtube vid=1YxYKmfL4SE] » read more

The Tao Of Software
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling and Pallab Chatterjee As software teams continue to race past hardware teams in numbers of engineers, hours spent on designs and NRE budgets, companies are beginning to question whether there needs to be a fundamental shift in priorities and strategy. The problem is that it takes far too long to write and debug the software and to get it working on the hardware, even with vir... » read more

5 Ways To Cut Power
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine. While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern ... » read more

Managing Physical Effects
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ann Steffora Mutschler Managing the physical effects from manufacturing is becoming increasingly critical as designs grow in size and process geometries dive lower. Just keeping track of these effects in a billion-gate design is a daunting task. At advanced manufacturing nodes, the capacitance and inductance effects make the design much harder—and that includes both on-die and off-die ... » read more

Low Power Simulation
By Luke Lang - 16 Jun, 2011 - Comments: 0

By Luke Lang Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP structural verification. But if it will help you sleep better at night, then go for it.” For the longer answer, keep reading. In order to run VDD/VSS-aware simulation, one must ha... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Who’s In Control?
By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there. Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA comp... » read more

EDA…Or Something Else?
By Atrenta - 26 May, 2011 - Comments: 0

The Design Automation Conference is almost here. That major focal point for the EDA industry where we gather to explain the present, predict the future, have a bunch of serious meetings and maybe a little fun, too. Some companies will stage an incremental update of their strategy and others will outline a major new strategy. This year, Atrenta will be talking strategy, with some announcement... » read more

Blog Review: May 25
By Ed Sperling - 25 May, 2011 - Comments: 0

By Ed Sperling Cadence’s Richard Goering follows Jim Hogan’s talk about the democratization of MEMS. This market is showing big gains lately, but to really release the emergency brake will require a different design approach. Mentor’s Robin Bornoff revs up the engine and turns on the neon underbody lighting in this look at the overclocking market, shifting effortlessly from cars to PC... » read more

Extraction, Power And Final Silicon
By Ed Sperling - 12 May, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor technology scales down, manufacturing effects are coming front and center, putting constant pressure on design teams to make sure that silicon can be modeled through the extraction process while performing analysis accurately. Extraction technology is one of the basic components needed to gain an accurate measurement of power, timing and signal int... » read more

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