tag: Cadence

The Real Value Of An LP Methodology
By Luke Lang - 12 May, 2011 - Comments: 0

By Luke Lang “What are some of the low-power mistakes that you have seen?” That is, by far, the most popular question asked by designers. And it’s a very good question. Why re-invent the wheel? Why repeat mistakes? It’s a lot easier to learn from someone else’s mistakes than from your own. Clearly, every company is different, and every design is different. But there are lots of co... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 06 May, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 29 Apr, 2011 - Comments: 0

Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE: When we move t... » read more

SoC Ecosystems Become More Tightly Integrated
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target. Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platfo... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Power Issues In 3D
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler The challenges associated with implementing IP subsystems range from maintaining a consistent I/O voltage, achieving consistency in metal stacks to managing a clock distribution network and creating adequate isolation between subsystems on a chip. It’s enough to make your brain hurt. Add to that 3D or 2.5D stacking and the engineering considerations grow substantial... » read more

Rationalization For Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ed Sperling Power budgets are becoming almost universally problematic. What used to be a unique headache for the cell-phone market has evolved into an ugly migraine that now includes everything with a battery—and increasingly even those devices that rely on a plug. The result is a cascade of effects that are widespread and growing. And while the drivers of this effort vary widely from ... » read more

RTL Power Estimation
By Luke Lang - 14 Apr, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about power estimation—finding the worst-case toggle rate to determine the worst-case power. This has been used very successfully by many designers to get an accurate estimation and analysis of power dissipation. These designers also are using the worst-case toggle rate to optimize power grid and meet dynamic IR drop requirements. With these power estim... » read more

Experts At The Table: Verification At 28nm And Beyond
By Ed Sperling - 14 Apr, 2011 - Comments: 0

Low-Power Engineering sat down to discuss issues in verification at 28nm and beyond with Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys, Ran Avinun, marketing group director at Cadence, Prakash Narain, president and CEO of Real Intent, and Lauro Rizzatti, general manager of EVE-USA. What follows are excerpts of that conversation. LPE: Power seems to... » read more

Verification At 28nm And Beyond
By Ed Sperling - 14 Apr, 2011 - Comments: 0

Low-Power Engineering looks at the challenges ahead in IC verification with Frank Schirrmeister of Synopsys, Ran Avinun of Cadence, Prakash Narain from Real Intent and Lauro Rizzatti from EVE. [youtube vid=bc5IhGrlJo4] » read more

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