tag: Cadence

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

Moore’s Law Revisited
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling The push to 20nm and beyond is creating some interesting gyrations in the EDA industry. While tools vendors continue to work on tools for the latest process nodes, they’re also taking some significant sidesteps. The first to publicly recognize a shift is under way was Cadence, which last year issued its EDA 360 manifesto. The strategy is to continue investing in existing to... » read more

Widening The Channels
By Ed Sperling - 17 Mar, 2011 - Comments: 0

By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

Fast LP Simulation
By Luke Lang - 17 Mar, 2011 - Comments: 0

By Luke Lang What are the most important features of a logic simulator? I’m sure there have been lots of surveys done for this question. Unfortunately, I can’t find any results on Google. Nevertheless, I would be willing to bet that fast performance is at or near the top of every verification engineer’s wish list. For the low-power verification engineers, fast performance is also a ke... » read more

The Growing Importance Of Subsystems
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling A growing reliance on third-party IP is beginning to expand well beyond just IP blocks and into full subsystems, opening significant growth opportunities for companies competing in this market as well as enormous business and technical challenges. The IP market is ripe for this kind of convergence. Complexity at advanced process nodes coupled with time-to-market demands has e... » read more

EDA Forecast: More Clouds
By Ed Sperling - 24 Feb, 2011 - Comments: 0

By Ed Sperling Design engineers and EDA vendors used to scoff at the idea of cloud-based tools, but no one is scoffing anymore. A decade after the idea of renting tools online fell flat, largely due to security concerns by chipmakers, all three of the major EDA players and some smaller rivals are taking cloud-based solutions very seriously again. There are several reasons for this change... » read more

Tailoring IP, Tools And Flows
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

What’s A Cell Phone?
By Ed Sperling - 27 Jan, 2011 - Comments: 0

By Ed Sperling Just because a smart phone is sold by Verizon or AT&T mobile no longer means that it will be used primarily as a phone. That distinction may sound trivial, but it has deep implications for the components that are used inside of these devices, how they’re used, and who wins the designs. Shifts such as this can also lead to broad changes in who buys the tools to develop t... » read more

Tailoring IP, Tools And Flows
By Ann Mutschler - 27 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler As SoC and system complexity rises continually and software drives much more in a system, specific vertical application areas will require tailored IP and tool flows to allow designers to meet time-to-market demands. Today, many systems are designed around a platform, which contains most of the STAR IP—processors, GPUs, memory controllers, interconnects, memory s... » read more

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