tag: Cadence

Power Model Complexity Grows
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ed Sperling The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months. The idea of modeling power is hardly new, but... » read more

Packaging’s Power Play
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects. IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. A... » read more

Golden Power Intent
By Luke Lang - 13 Jan, 2011 - Comments: 0

By Luke Lang A few months ago, I wrote about the rapid adoption of the power intent file for low-power designs. While this is certainly a step in the right direction, some design teams may be taking several steps backwards by not treating the power intent file with the proper respect. For example, I have seen one case where the verification, synthesis, and backend implementation teams each had... » read more

The Challenge Of Packaging
By Ann Mutschler - 13 Jan, 2011 - Comments: 0

Semiconductor packaging isn’t a sexy subject, and it’s one that’s been largely overlooked by the design community. Until now, that is. I recently spoke with Brad Griffin at Cadence, who stressed that managing the power through packages even on a single die is still one of the most challenging things engineers must navigate. “As people integrate more technology into a single chip o... » read more

Blog Review: Jan. 5
By Ed Sperling - 05 Jan, 2011 - Comments: 0

By Ed Sperling Mentor’s Robin Bornoff returns to his beer fridge with a New Year’s resolution for sobriety and a revelation that an empty refrigerator never cools as well as a full one. Well, there’s always Diet Coke and double-shot iced espresso. Cadence’s Tom Anderson sheds some long overdue light on the famous processor “divide bug” that generated mostly right answers. This o... » read more

Supply Chain Adjusts To Design At The System Level
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler System-level design is impacting the supply chain at many levels. Software suppliers, IP providers, semiconductor companies, system integrators and OEMs are challenged to work ever more closely together and find a new balance of power for who controls what in the content of an SoC. “We see more and more the design chain driving how our tools work together,” Fra... » read more

System-Level Technology Conversations Shift To Deployment
By Ann Mutschler - 16 Dec, 2010 - Comments: 0

While much has been achieved to define a system-level design flow, more is still needed. Technology goals vary depending on the perspective of tool providers in terms of what needs to be done to realize the promise of a streamlined tool flow from TLM 2.0 down to GDS II. To many, 2011 will be an interesting year in the system-level design space as conversations with customers have shifted. �... » read more

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

What’s Your Toggle Rate?
By Luke Lang - 02 Dec, 2010 - Comments: 0

By Luke Lang Now that power is a key specification, designers are looking into various design techniques to reduce power. One thing that designers realize very quickly is that there is a cost associated with these low-power techniques. Some of these costs are silicon area and design complexity. Very quickly, designers face the tradeoff of cost vs. power saving. In order to analyze this tradeof... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

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