tag: chiplet security

Side-Channel Risks Across 2.5D/3D Integration and Chiplet-Based Systems (Grenoble INP – UGA et al.)
By Technical Paper Link - 25 May, 2026 - Comments: 0

Researchers from Grenoble INP - UGA, CNRS, TIMA have released “Spying Across Chiplets: Side-Channel Attacks in 2.5/3D Integrated Systems”. Abstract “Advanced packaging and chiplet-based integration are increasingly adopted to build complex heterogeneous systems beyond the limits of monolithic scaling. While these architectures offer major benefits in terms of modularity, yield, a... » read more

Securing AI at the Silicon Level: Solutions for a Smarter, Safer Future
By Synopsys - 06 May, 2026 - Comments: 0

This white paper explains how Synopsys Security IP embeds hardware‑rooted protection into AI SoCs and chiplets to secure their data and models. It highlights growing AI attack vectors across edge and data‑center environments and shows how technologies like PUF, tRoot HSM, interface security, and PQC create long‑term, silicon‑level trust. Why read this whitepaper: Learn how sili... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Cyber Threats Multiply With Commercial Chiplets
By Ann Mutschler - 01 May, 2025 - Comments: 0

The commercialization of chiplets will significantly boost the potential for attacks on hardware, requiring a much broader set of security measures and processes at every level of the supply chain, including traceability from initial design to end of life. Much progress has been made in recent years on security measures, including everything from identifying unusual data traffic inside a chi... » read more

On-Chiplet Framework for Verifying Physical Security and Integrity of Adjacent Chiplets
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification" was published by researchers at Worcester Polytechnic Institute. Abstract "The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a singl... » read more

Multi-Party Computation for Securing Chiplets
By Technical Paper Link - 12 Mar, 2025 - Comments: 0

A new technical paper titled "Garblet: Multi-party Computation for Protecting Chiplet-based Systems" was published by Worcester Polytechnic Institute. Abstract "The introduction of shared computation architectures assembled from heterogeneous chiplets introduces new security threats. Due to the shared logical and physical resources, an untrusted chiplet can act maliciously to surreptitiousl... » read more

Systems-in-Package: Authenticated Partial Encryption Protocol For Secure Testing (U. of Florida)
By Technical Paper Link - 12 Nov, 2024 - Comments: 0

A new technical paper titled "GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package" was published by researchers at University of Florida and University of Central Florida. Abstract: "A heterogeneous integrated system in package (SIP) system integrates chiplets outsourced from different vendors into the same substrate for better performance. However, during post-integra... » read more

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