The Painful Reality Of Scaling Cloud AI


The shift to Generative AI (GenAI) has overwhelmed existing infrastructure, transforming previously rare issues into daily operational realities. Skyrocketing costs, intense energy consumption, and hardware failures at unprecedented scales illustrate the strain of current AI workloads. With models like GPT-4 costing tens of millions and GPT-5 projected to surpass a billion-dollar threshold, the... » read more

Transforming Test For Co-packaged Optics


Data centers are undergoing a dramatic transformation to reduce the power consumption of high-speed data transmissions by 70% or more with co-packaged optics. By moving optical transceivers from the fronts of racks into the same package as the networking switch and HBMs, AI programs that used to take a week to run can now be completed in a day. To enable this change in production manufacturi... » read more

UEC-LLR: The Future Of Loss Recovery In Ethernet For AI And HPC


As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become the backbone of modern data centers, they generate and consume a massive amount of data. Traditional Ethernet was not built for such high-bandwidth traffic. In HPCs and AI models, computations are distributed across the nodes and the data is shared in real time with low latency and lossless communication. As ... » read more

For Chip Developers, HW/SW Co-Design Key To Data Center Efficiency


Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI's power consumption. Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-so... » read more

Scaling In The AI Era: The Role Of PCI Express 7.0 Switches In Next-Gen Data Centers


As artificial intelligence (AI) workloads continue to scale in complexity and volume, the infrastructure that supports them must evolve just as rapidly. At the heart of this transformation lies PCI Express 7.0 (PCIe 7.0), a next-generation interconnect standard that is redefining how data moves within high-performance computing (HPC) and AI-driven data centers. PCIe 7.0 doubles the raw bit r... » read more

Designing The AI Factories: Unlocking Innovation With Intelligent IP


The rapid evolution of artificial intelligence (AI) is reshaping the technological landscape, driving unprecedented demands on computing infrastructure. At the heart of this transformation lie innovations in intellectual property (IP) that enable scalable, efficient, and performance-driven AI factories. These advancements are central to addressing the technical challenges of modern AI workloads... » read more

Co-Designing Data Center Architecture To Support LLMs (Intel, Georgia Tech)


A new technical paper titled "Scaling Intelligence: Designing Data Centers for Next-Gen Language Models" was published by Intel Corporation and Georgia Tech. An excerpt from the paper's abstract: "Our work provides a comprehensive co-design framework that jointly explores FLOPS, HBM bandwidth and capacity, multiple network topologies (two-tier vs. FullFlat optical), the size of the scale-ou... » read more

Optical Interconnectivity At 224 Gbps


AI is generating so much traffic that traditional copper-based approaches for moving data inside a chip, between chips, and between systems, are running out of steam. Just adding more channels is no longer viable. It requires more power to drive signals, and the distance those signals can travel without excessive loss is shrinking. Mike Klempa, product marketing specialist at Alphawave Semi, di... » read more

Future-proofing AI Models


Experts At The Table: Making sure AI accelerators can be updated for future requirements is becoming essential due to the rapid introduction of new models. Semiconductor Engineering sat down to discuss the challenges of future-proofing these designs with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vic... » read more

AI Accelerators Moving Out From Data Centers


Experts At The Table: The explosion in AI data is driving chipmakers to look beyond a single planar SoC. Semiconductor Engineering sat down to discuss the need for more computing and the expanding role of chiplets with Marc Meunier, director of ecosystem development at Arm; Jason Lawley, director of product marketing for AI IP at Cadence; Paul Karazuba, vice president of marketing at Expedera; ... » read more

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