tag: electromigration

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

TSVs: Copper, Silicon, And CTE Mismatch
By Katherine Derbyshire - 23 Jun, 2016 - Comments: 3

As previous articles in this series have discussed, advanced packages introduce new materials and new reliability concerns. Diffusion into solder bumps can create brittle, high resistance, intermetallic compounds. Heat transfer through an interposer can degrade the lifetime of even cool, low power chips. Still, through-silicon vias are unique in that they cut directly through the integrated cir... » read more

Electromigration: Not Just Copper Anymore
By Katherine Derbyshire - 31 May, 2016 - Comments: 2

While integrated circuit manufacturers have worried about electromigration for a long time, until recently most of their concerns have focused on the on-chip interconnects. The larger dimensions found in integrated circuit packages have, in most cases, improved heat dissipation, reduced current density, and eliminated most [getkc id="160" kc_name="electromigration"] risks. Over the last sev... » read more

Keeping The Whole Package Cool
By Katherine Derbyshire - 12 May, 2016 - Comments: 0

Heat dissipation is a critical issue for designers of complex chip-stacking and system-in-package devices. The amount of heat generated by a device increases as the number of transistors goes up, but the ability to dissipate the heat depends on the package surface area. Because the goal of 3D packaging is to squeeze more transistors into less overall space, new heat dissipation issues are em... » read more

Analyzing The Integrity Of Power
By Ann Mutschler - 14 Apr, 2016 - Comments: 0

Power analysis is shifting much earlier in the chip design process, with power emerging as the top design constraint at advanced process nodes. As engineering teams pack more functionality and content into bigger and more complex chips, they are having to deal with more complex interactions that affect everything from power to its impact on signal integrity and long-term reliability. That, i... » read more

Pain Points At 7nm
By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

Predictions For 2016: Semiconductors, Manufacturing And Design
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Thinking Outside The Chip
By Ed Sperling - 14 Jan, 2016 - Comments: 0

Intel will begin adding 2.5D and 3D packaging into its processors, following the lead set by IBM and AMD in recognizing that new packaging approaches are essential for improving performance and lowering power. This shift won't derail the semiconductor industry's efforts to the reach future process nodes or continually shrink features, but it does add context for other factors that in... » read more

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