Keeping Up With The Productivity Challenge


Until recently, EDA software rode the coattails of increasing processor performance as part of its drive to continue providing faster and more powerful development software to the people designing, among other things, the next generation of faster processors. It was a fortuitous ring. Around the turn of the century, with the migration to multi-core computing systems, all of that changed. In ord... » read more

A Dream For The Future Of Real System-Level Design Validation


"I have a dream…that one day…all SoCs will be free…of bugs and verifying them will be a walk in the park. I have a dream…that one day…all software engineers will be able to validate their software on pre-silicon hardware at the speed of light, delivering fully functional embedded software “before-on-time” for tape-out. I have a dream today…Well, if not today, how about first ... » read more

Blog Review: Oct. 29


Ansys' Bill Vandermark uncovers the top engineering articles for the week. Check out the tractor beam in Australia that can push and pull objects and Naim's soundbar that may act like a gateway drug to bankruptcy. It may sound counterintuitive, but ARM's Jakub Lamik draws a direct link between bandwidth consumption and power consumption and explains that's the case. Samsung's Farhad Tab... » read more

Legal Battlefield In Emulation


Given the rate of research and development within the EDA industry, you might expect it to be a highly litigious industry, but apart from theft claims, there have not been that many law suits brought to bear – except in the area of [getkc id="30" comment="emulation"]. Emulation has, since its early days in the early 1990s, always been a legal battlefield, and the hostilities continue to this ... » read more

When To Use Simulation, When To Use Emulation


Should you emulate or simulate? In this brief historical review, Dr. Lauro Rizzatti compares the two and reveals when to use which and explains why only emulation can verify embedded SW in an SoC design. To read more, click here. » read more

High-Level Gaps Emerge


Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow with Bernard Murphy, CTO at [getentity id="22026" e_name="Atrenta"]; Leah Clark, associate technical director for digital video technology at Broadcom; Phil Bishop, vice president of the system level design system & verification group at [getentity id="22032" e_name="Cadence"]; and Jon McDon... » read more

The Week In Review: Design


Tools Synopsys rolled out a hybrid verification platform, which it said can shave months off design time. The platform acts like a bridge between emulation, FPGA prototyping, simulation, static and formal verification and debug. Mentor Graphics uncorked a new version of its embedded hypervisor, which includes better system configuration, debugging and hardware support. The hypervisor is aim... » read more

How To Cut Verification Costs For IoT


Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Leveraging Virtual Prototypes For Hybrid Emulation


As highlighted in many of my blog posts, virtual prototyping has really established itself as the key methodology to shift left software development by decoupling the dependency of software development from hardware availability. The success of the “Better Software. Faster!” book illustrates the wide spread interest in the methodology. The success of virtual prototypes also has led users... » read more

Extending Power Analysis To The Emulation of Complex SoCs


Using hardware emulation to estimate SoC power consumption delivers significant value. Emulators are capable of long runs on large designs, making it practical to emulate an RTOS boot sequence or graphics processing of multiple frames. Estimating power consumption of these advanced functions executing across the complete SoC provides valuable insight into the chip’s power draw and its impact ... » read more

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