tag: emulation

The Agony Of Hardware-Assisted Development Choices
By Frank Schirrmeister - 24 Jul, 2014 - Comments: 0

“When defining a product, if you haven’t upset at least one part of the organization, then the product is probably ill defined and tries to address too many things!” That’s what one of my mentors taught me early on in my career as product manager. Ever since then I have been interested in portfolio management. The most recent announcement that we made on the Protium Rapid Prototyping Pl... » read more

New Uses For Emulation
By Ed Sperling - 16 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

New Uses For Emulation
By Ed Sperling - 29 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

New Uses For Emulation
By Ed Sperling - 22 May, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss the changing emulation landscape with Jim Kenney, director of marketing for emulation at Mentor Graphics; Tom Borgstrom, director of the verification group at Synopsys; Frank Schirrmeister, group director of product marketing for the System Development Suite at Cadence; Gary Smith, chief analyst at Gary Smith EDA; and Lauro Rizzatti, a verification ... » read more

Executive Insight: Wally Rhines
By Ann Mutschler - 05 May, 2014 - Comments: 1

Semiconductor Engineering sat down with Wally Rhines, chairman and CEO of Mentor Graphics, to discuss what is required for EDA to grow, key areas of opportunity for EDA growth and going against the grain. The interview is part of an ongoing series of in-depth interviews with top executives from all segments of the industry. SE: What keeps you awake at night? Rhines: Actually nothing keeps... » read more

Localized, System-Level Protocol Checks And Coverage Closure
By Various Writers - 23 Apr, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

How To Speed Up Verification
By Ann Mutschler - 30 Jan, 2014 - Comments: 0

Software requirements have changed the tapeout process in today’s SoCs so much that it isn’t uncommon to hear a design can’t be released because Android hasn’t booted. “It’s one of those things where you really understand that what used to be classic hardware verification that said ‘the chip is done’ is heavily impacted by if it actually does software things,” noted Frank S... » read more

Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
By Various Writers - 29 Jan, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Blog Review: Jan. 29
By Ed Sperling - 29 Jan, 2014 - Comments: 0

ARM’s Ellie Stone returns from the Mobile Games Forum in London with some insights about where the future competition will come from. No. 4 on her list is the big surprise. Cadence’s Brian Fuller has unearthed an old black & white AT&T video that makes you wonder how they created wire. So that’s what happens when you heat a semiconductor with a Bunsen burner. What’s the real val... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

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