tag: EUV

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Four Factors Driving Processor Choices
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Choosing processors for an SoC, a system-in-package, or even a complete system is becoming much more difficult, and the challenge is growing as demands on performance, power, area and time to market continue to increase. There are many reasons why this is becoming more difficult—and some designs will require more tradeoffs than others, depending upon IP re-use or a particul... » read more

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

Fallback Plans
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With EUV lithography missing a few deadlines already, the semiconductor industry has begun to search for alternatives. None of these solutions is simple, of course, and it’s questionable whether they’re even economically viable. And even if EUV is ready for mass production by 14nm, there are new challenges that have to be dealt with—particularly in the space... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

Bucket Lists
By Ed Sperling - 26 Jun, 2012 - Comments: 0

At 130nm, the introduction of copper interconnects, 300mm wafers and low-k dielectrics left the entire supply chain breathless. There had never been as many changes at a single process node in the history of semiconductors. At 28nm, the number of changes will pale compared to what’s necessary at 20nm, and that will pale to what’s required at 14nm. But unlike 130nm, when most of those cha... » read more

Aloha Lithography!
By Chris Mack - 10 Jun, 2012 - Comments: 0

An excuse to travel to Hawaii?  You don’t have to ask me twice.  Especially if it is the Big Island, my favorite of the Hawaiian isles.  My excuse this time?  The 3-beams conference, also called triple-beams, EIPBN, or occasionally (rarely) the International Conference on Electron, Ion and Photon Beam Technology & Nanofabrication. The conference was held last week (May 29 – June ... » read more

The Hidden Costs Of Directed Self-Assembly
By Ed Sperling - 29 May, 2012 - Comments: 2

By Mark LaPedus Directed self-assembly (DSA) has been billed by some as a potential paradigm shift in semiconductor manufacturing, but it may not turn out to be quite the panacea its proponents suggest—or at least not yet. There are many questions surrounding DSA, an alternative lithography technology that makes use of block copolymers to enable fine pitches. Key among those questions ar... » read more

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