New Deep Learning Processors, Embedded FPGA Technologies, SoC Design Solutions


Some of the most valuable events at DAC are the IP Track sessions, which give small and midsize companies a chance to share innovations that might not get much attention elsewhere. The use of IP in SoCs has exploded in recent years. In a panel at DAC 2017, an industry expert noted that the IP market clearly was growing even faster than EDA itself, due to the fact that more and more chip mak... » read more

Challenges At The Edge


By Kevin Fogarty and Ed Sperling Edge computing is inching toward the mainstream as the tech industry begins grappling with the fact that far too much data will be generated by sensors to send everything back to the cloud for processing. The initial idea behind the IoT/IIoT, as well as other connected devices, was that simple sensors would relay raw data to the cloud for processing throug... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Tech Talk: eFPGA Timing


Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

Designing 5G Chips


5G is the wireless technology of the future, and it’s coming fast. The technology boasts very high-speed data transfer rates, much lower latency than 4G LTE, and the ability to handle significantly higher densities of devices per cell site. In short, it is the best technology for the massive amount of data that will be generated by sensors in cars, IoT devices, and a growing list of next-g... » read more

The Week In Review: Design


Tools & IP Cadence unveiled its latest DSP for embedded vision and AI, Tensilica Vision Q6 DSP. The DSP is built on a 13-stage processor pipeline and new system architecture designed for use with large local memories, and achieves 1.5GHz peak frequency and 1GHz typical frequency at 16nm. Compared to its predecessor, it offers 1.5X greater vision and AI performance than its predecessor and ... » read more

Introduction To eFPGA Software


In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software. An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC. The clock(s) for the eFPGA come from the SoC. The configuration of the eFPGA is done by the SoC... » read more

Tiling Is Critical For eFPGA Users: ArrayLinx Delivers


FPGA chips come in multiple sizes — modular blocks of programmable logic, DSP MACs and RAM are intermixed in different sizes and ratios then stitched together with top-level interconnect, clocking, etc and surrounded by a ring of I/Os like GPIO, SerDes, USB, etc. There is extensive engineering and top-level physical design for each distinct FPGA array and chip. eFPGA is different: Custome... » read more

The Bumpy Road To 5G


5G is coming, but not everywhere, not all at once, and not the fastest version of this technology right away. In fact, the probable scenario is that 5G will be rolled out first in densely populated urban areas, starting in 2020 or 2021, with increasingly widespread adoption over the next decade after that. But 5G is unlikely to ever completely replace 4G LTE, just as a smart phone today roll... » read more

IP And Power


[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

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