Simulations of Silicon Spin Qubits Based on a GAAFET (Teikyo U., Riken)


A new technical paper, "Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor," was published by Teikyo University and RIKEN. Abstract "We theoretically investigated the readout process of a spin–qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configuration... » read more

GAA Transistors: 3D Atomic-Scale Metrology of Strain Relaxation and Roughness via Electron Ptychography (Cornell, ASM, TSMC)


A new technical paper titled "3D Atomic-Scale Metrology of Strain Relaxation and Roughness in Gate-All-Around (GAA) Transistors via Electron Ptychography" was published by researchers at Cornell University, ASM and TSMC. Abstract "To improve transistor density and electronic performance, next-generation semiconductor devices are adopting three-dimensional architectures and feature sizes dow... » read more

FinFETs Give Way To Gate-All-Around


When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

Gaps In Metrology Could Impact Yield


For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more