tag: hybrid bonding

3DIO IP For Multi-Die Integration
By Lakshmi Jain - 17 Oct, 2024 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithogra... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs
By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

Defect Challenges Grow At The Wafer Edge
By Laura Peters - 10 Sep, 2024 - Comments: 0

Reducing defects on the wafer edge, bevel, and backside is becoming essential as the complexity of developing leading-edge chips continue to increase, and where a single flaw can have costly repercussions that span multiple processes and multi-chip packages. This is made more difficult by the widespread rollout of such processes as hybrid bonding, which require pristine surfaces, and the gro... » read more

3.5D: The Great Compromise
By Ed Sperling - 21 Aug, 2024 - Comments: 1

The semiconductor industry is converging on 3.5D as the next best option in advanced packaging, a hybrid approach that includes stacking logic chiplets and bonding them separately to a substrate shared by other components. This assembly model satisfies the need for big increases in performance while sidestepping some of the thorniest issues in heterogeneous integration. It establishes a midd... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

What’s Changing In DRAM
By Ed Sperling - 22 Jan, 2024 - Comments: 0

More data requires more processing and more storage, because that data needs to be stored somewhere. What’s changing is that it’s no longer just about SRAM and DRAM. Today, multiple types of DRAM are used in the same devices, each with its own set of tradeoffs. C.S. Lin, marketing executive at Winbond, talks about the potential problems that causes, including mismatches in latency, and high... » read more

Many More Hurdles In Heterogeneous Integration
By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Making Heterogeneous Integration More Predictable
By Ed Sperling - 29 Nov, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Gearing Up For Hybrid Bonding
By Laura Peters - 23 Oct, 2023 - Comments: 2

Hybrid bonding is becoming the preferred approach to making heterogeneous integration work, as the semiconductor industry shifts its focus from 2D scaling to 3D scaling. By stacking chiplets vertically in direct wafer-to-wafer bonds, chipmakers can leapfrog attainable interconnection pitch from 35µm in copper micro-bumps to 10µm or less. That reduces signal delay to negligible levels and e... » read more

Negative-Tone Photosensitive Polymeric Bonding Material To Enable Room Temperature Prebond For Cu/Polymer Hybrid Bonding
By Brewer Science - 18 Oct, 2023 - Comments: 0

An evaluation of a negative-tone i-line photosensitive polymeric bonding material for achieving prebonding in Cu/polymer hybrid bonding at low temperatures via the Cu damascene process. The polymeric material has a Tg≤100∘C ; Young’s modulus of 99 MPa, the dielectric constant of 2.6, and dissipation factor of 0.0016 at 10 GHz. Shear tests revealed a bond shear strength of over 10 MPa when... » read more

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