tag: imec

Shades Of Green
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler Ask five people in the electronics industry what ‘green’ means and you are sure to get five different answers. In the datacenter, the definition is a little clearer because big iron draws so many amps. But at the SoC level where does the industry stand? The answer is as multifaceted as an SoC itself, with some answers based more on one-upmanship than real met... » read more

Design-For-DSA Industry Begins To Assemble
By Mark LaPedus - 18 Apr, 2013 - Comments: 0

By Mark LaPedus The industry is aggressively pursuing directed self-assembly (DSA) as an alternative patterning technology for future chip designs. DSA, which enables fine pitches through the use of block copolymers, is in the R&D pilot line stage today. The fab tools, process flows and materials are basically ready, but there are still several challenges to bring the technology from th... » read more

Directed Self-Assembly Grows Up
By Mark LaPedus - 21 Mar, 2013 - Comments: 1

By Mark LaPedus At last year’s SPIE Advanced Lithography conference, Christopher Bencher, a member of the technical staff at Applied Materials, said the buzz surrounding directed self-assembly (DSA) technology resembled the fervor generated at the famous Woodstock rock concert in 1969. This was clearly evident from the tumultuous and free-flowing movement that threatened the status quo o... » read more

Getting Ready For High-Mobility FinFETs
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

What Will Replace Dual Damascene?
By Mark LaPedus - 24 Jan, 2013 - Comments: 0

By Mark LaPedus In the mid-1990s, IBM announced the world’s first devices using a copper dual damascene process. At the time, the dual damascene manufacturing process was hailed as a major breakthrough. The new copper process enabled IC makers to scale the tiny interconnects in a device, as the previous material, aluminum, faced some major limitations. Dual damascene remains the workhorse... » read more

Welcome To The ‘Probably Good Die’ Era
By Mark LaPedus - 13 Dec, 2012 - Comments: 0

By Mark LaPedus In today’s systems, consumers want more performance and bandwidth with a longer battery life. Some chip segments are keeping up with the demands. Still other areas are falling way behind the curve. Battery life is an obvious problem, but memory bandwidth is under the radar. “Initially, memory bandwidth nearly doubled every two years, but this trend has slowed over the pa... » read more

Mobile Memory Madness
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap. As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architectur... » read more

SPOTLIGHT ON FD-SOI, FINFETS AT IEEE SOI CONFERENCE
;1-4 OCT, NAPA
By Various Writers - 25 Sep, 2012 - Comments: 0

The 38th annual SOI Conference is coming right up. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications. Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the ... » read more

Power And Performance: GSS Sees SOI Advantages For FinFETs
By Various Writers - 17 Sep, 2012 - Comments: 0

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage,Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI. To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s... » read more

The Threat Within
By Applied Materials Writers - 16 Aug, 2012 - Comments: 0

By Connie Duncan Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called via... » read more

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