tag: IP

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 22 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Sprint To The Finish Line
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss future challenges, pain points, and how the supply chain is being reconfigured with Chi-Ping Hsu, senior vice president for R&D in the Silicon Realization Group at Cadence. What follows are excerpts of that conversation. LPHP: How important is it to be at the front end of Moore’s Law? Hsu: Strategically, it’... » read more

Guesswork, And Other Design Paradigms
By Bernard Murphy - 14 Mar, 2013 - Comments: 0

PPA for soft IP seems like an oxymoron. How do you determine the implementation characteristics (PPA — Power, Performance and Area) for something that has not yet been implemented? Flying blind until implementation would be a rookie move. More likely you are going to estimate based on a prior implementation. Not a bad approach if the IP hasn’t changed significantly and the target library is... » read more

Let The IP Wars Begin
By Ed Sperling - 14 Mar, 2013 - Comments: 0

y Ed Sperling Nature abhors a vacuum. Customers abhor a monopoly. It appears both problems are now being solved in the EDA world—assuming approval by regulatory agencies, of course. There have been two concerns facing chipmakers in regards to third-party IP. One is political. Most large companies spent millions of dollars and thousands of frustrating man-hours developing their own interna... » read more

Surprises Abound As Subsystem IP Gains Prominence
By The SE Staff - 28 Feb, 2013 - Comments: 0

What’s new in the world of subsystem intellectual property? To find out, System-Level Design sat down with Richard Wawrzyniak, senior market analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation. SLD: You mentioned that the cost of semiconductor intellectual property (IP) at 20nm and below is increasing. Why is that? Wawrzyniak: The reason is c... » read more

Advanced SoC Interconnect IP
By Kurt Shuler - 28 Feb, 2013 - Comments: 0

By Kurt Shuler I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year. But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward. The one lesson learned is that flexibility for SoC designs is increasingly more important. In ... » read more

Raising The Stakes For IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

By Ed Sperling As the amount of IP in an SoC increases, so do the number of players who want to strengthen their position in this market. The big acquisitions that began several years ago over time have proved to be just opening salvos—something that was impossible to predict when this shift began. Synopsys’ purchase of Virage Logic and Cadence’s purchase of Denali, both of which occu... » read more

Proving IP
By Ed Sperling - 14 Feb, 2013 - Comments: 0

As the amount of commercially available IP in a design increases, so does the level of confusion. Unlike those giant yellow stickers you get with a major appliance that tell you how much energy you’re likely to use over the course of a year and the projected cost range, there’s no such information available for semiconductor IP. In fact, there’s even resistance to provide that kind of ... » read more

The Integrated IP Subsystem: A Converging SoC Solution
By Various Writers - 31 Jan, 2013 - Comments: 0

The consumer device market is witnessing incredible market space convergence between mobile handheld, automotive, and home electronics. IP vendors, engineers, and system design engineers face a multitude of challenges when designing and developing ICs, systems, or subsystems for the next great portable device. The next cell phone for instance, will not only be a multimedia player, but also a de... » read more

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