Addressing The Challenges Of IoT Design


Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. The Tanner design flow is architected to seamlessly work in any of these design domains by employing an integrated design flow for desi... » read more

Raising The IQ Of Your MEMS-Based IC Design Flow


By Nicolas Williams and Qi Jing Internet of Things (IoT) applications depend on smart objects that interact with the real world. So your IoT project is likely to contain ICs that integrate micro electro-mechanical systems (MEMS), such as accelerometers, pressure sensors, motors, and microphones that acquire data for analysis. These projects are finding their way into automobiles, phones, and... » read more

Tear Down The Wall Between Front-End And Back-End Teams


As complexity of system-on-chip devices increases, it's becoming imperative for design teams and organizations to re-examine how they work with one another in order to improve productivity. One giant step in this direction is to bridge the divide between the front-end design process and the physical back-end design process. We often refer to this as a figurative “wall,” but there is real... » read more

Signal Integrity Issues


Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

The Week In Review: July 12


By Ed Sperling Cadence rolled a new version of its layout suite of tools for electrically aware designs, allowing design teams to check on electrical issues while the layout is being done. The company says this can reduce circuit design time by up to 30%, in addition to optimizing for performance and area. Cadence also announced a deal with Global Unichip, which successfully taped out a 20nm ... » read more

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