tag: Mentor

Multicore Debug Evolves To The System-Level
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The proliferation and expansion of multicore architectures is making debug much more difficult and time-consuming, which in turn is increasing demand for more comprehensive system-level tools and approaches. Multicore/multiprocessor designs are the most complex devices to debug. More interactions and interdependencies between cores mean more things possibly can go wrong. In fact, so many pro... » read more

Evaluate ESD Robustness With Cell-Based P2P/CD Verification
By Mentor, a Siemens Business - 21 Dec, 2020 - Comments: 0

Detecting and verifying an ESD structure can be challenging for designers without specialized ESD experience. The Calibre PERC reliability platform offers cell-based P2P and CD checks that can be used to quickly, accurately, and easily evaluate ESD robustness without the need for advanced ESD expertise. To read more, click here. » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Dec, 2020 - Comments: 0

Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Blog Review: Dec. 16
By Jesse Allen - 16 Dec, 2020 - Comments: 0

Arm's Benoit Labbe investigates why battery monitoring is so important for a low-power microcontroller and shows how it was implemented in the M0N0 MCU while drawing a fraction of a nW in typical conditions. Siemens EDA's Harry Foster takes a look at how much of their time FPGA design engineers spend on verification, and the tasks that keep verification engineers the busiest. Synopsys' Sc... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 11 Dec, 2020 - Comments: 0

Automotive Self-driving car company Cruise now has driverless cars on the streets of San Francisco, Calif., reports the San Francisco Chronicle. Cruise, which is backed by General Motors, is testing five driverless cars in the urban — and very hilly — environment of San Francisco. Cruise is using an EV — the Chevy Bolt — as a test vehicle. At Level 4 driving, the cars will not have a w... » read more

Fast, Low-Power Inferencing
By Russell Klein - 10 Dec, 2020 - Comments: 1

Power and performance are often thought of as opposing goals, opposite sides of the same coin if you will. A system can be run really fast, but it will burn a lot of power. Ease up on the accelerator and power consumption goes down, but so does performance. Optimizing for both power and performance is challenging. Inferencing algorithms for Convolutional Neural Networks (CNN) are compute int... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Low Power Still Leads, But Energy Emerges As Future Focus
By Ann Mutschler - 10 Dec, 2020 - Comments: 1

In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

An Integrated Approach To Power Domain And Clock Domain Crossing Verification
By Mentor, a Siemens Business - 09 Dec, 2020 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power control... » read more

Blog Review: Dec. 9
By Jesse Allen - 09 Dec, 2020 - Comments: 0

Arm's Benoit Labbe digs into designing a power converter for Arm Research's ultra-low power M0N0 microcontroller, with a focus on optimal efficiency and leakage constraints. Mentor's Harry Foster tries to get a sense of how much effort is spent in verification of FPGAs by looking at the amount of time spent and number of engineers on a project. Cadence's Paul McLellan listens in as Odile ... » read more

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