Week In Review: Design, Low Power


Tools & IP Synopsys debuted VIP and a UVM source code test suite for IP supporting Ethernet 800G. The VIP supports DesignWare 56G Ethernet, 112G Ethernet, and 112G USR/XSR PHYs for FinFET processes, which can be integrated for 800G implementations based on 8 lane x 100 Gb/s technology. The VIP can switch speed configurations dynamically at run time and includes a customizable set of frame ... » read more

What’s Changing, What Isn’t


The global pandemic is creating economic chaos on a global scale. The big question now is when the coronavirus is brought under control, and just how long its effects will extend beyond the current health crisis. For the semiconductor industry, which has weathered many long and deep financial swings, this one at least is finite. When the virus stops spreading, or when treatments are availabl... » read more

Why It’s So Hard To Create New Processors


The introduction, and initial success, of the RISC-V processor ISA has reignited interest in the design of custom processors, but the industry is now grappling with how to verify them. The expertise and tools that were once in the market have been consolidated into the hands of the few companies that have been shipping processor chips or IP cores over the past 20 years. Verification of a pro... » read more

EDA In The Cloud


Interest in the use of third-party public clouds in conjunction with electronic design automation (EDA) applications has never been higher. Back in February, Ed Sperling and I did a video interview (embedded below) to discuss EDA and cloud computing. This article follows up on that interview, providing some additional insight into why and how the integrated circuit (IC) industry reached this po... » read more

Reducing IR And EM Issues With Automated Via Insertion


IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Blog Review: March 25


Rambus' Steven Woo checks out common memory systems that are used in the highest performance AI applications and points to the differences between on-chip memory, HBM, and GDDR. Mentor's Colin Walls considers whether software for embedded systems should be delivered as a binary library or source code and warns of some key potential issues when requesting source code. A Synopsys writer poi... » read more

Blog Review: March 18


Arm's Divya Prasad investigates whether power rails that are buried below the BEOL metal stack and back-side power delivery can help alleviate some of the major physical design challenges facing 3nm nodes and beyond. Rambus' Steven Woo takes a look at a Roofline model for analyzing machine learning applications that illustrates how AI applications perform on Google’s tensor processing unit... » read more

Aging Analysis Standard Solidifies Through Collaborative Effort


By Ahmed Ramadan, Greg Curtis, Harrison Lee, Jongwook Kye, and Sorin Dobre We live in a connected world and it is estimated that by 20251 the total amount of worldwide data will swell to 163 ZB, or 163 trillion gigabytes. This rapid growth in data expansion is driving an explosion in new designs and new requirements for consumer, data center, automotive, and Internet of Things (IoT) applicat... » read more

The Long Road To Quantum Computing


Building a quantum computer is like building a cathedral. They both take a couple generations. The time frame for useful quantum computing applications that are not toy-sized is still a few years to a decade or more away. But the push is on now. Governments are racing to get their country’s quantum computing going for national security reasons. Companies such as Google and IBM are competin... » read more

Machine Learning At The Edge


Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet n... » read more

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