Formal Apps Take The Bias Out Off Functional Verification


The Questa Formal Apps automate common formal analysis tasks, providing a multiple set of tools for formal verification experts and novices alike. Each of these automated tasks are integrated into a holistic, formal analysis workflow that allows you to use what you need when you need it. This paper describes common verification challenges and how specific Questa Formal Apps handle them along wi... » read more

Blog Review: Mar. 27


Rambus' Steven Woo takes a look at the memory requirements of neural networks and why some companies are using on-chip memory while others are using HBM2 or GDDR6. Cadence's Lana Chan  observes growing momentum for NVMe and highlights some new features in the latest specification that are pushing mainstream adoption forward. Mentor's Matthew Ballance contends that when it comes to adopti... » read more

Single Vs. Multi-Patterning EUV


Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

Blog Review: Mar. 20


Cadence's Paul McLellan argues that rapid improvements in the performance of general-purpose computing led to a lack of innovation in domain-specific architectures, but as scaling slows, they're entering a new golden age. In a video, Mentor's Colin Walls takes a look at the use of floating point in an embedded application and some of the pitfalls associated with it. Synopsys' Taylor Armer... » read more

The Growing Challenge Of Thermal Guard-Banding


Guard-banding for heat is becoming more difficult as chips are used across a variety of new and existing applications, forcing chipmakers to architect their way through increasingly complex interactions. Chips are designed to operate at certain temperatures, and it is common practice to develop designs with some margin to ensure correct functionality and performance throughout the operat... » read more

Using Less Power At The Same Node


Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study


As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the more we know about the bigger picture, context, historical and projected trends, or simply how other people are doing the same thing, the more efficiently and successfully we can do our jobs. Prov... » read more

Memory Tradeoffs Intensify in AI, Automotive Applications


The push to do more processing at the edge is putting a strain on memory design, use models and configurations, leading to some complex tradeoffs in designs across a variety of markets. The problem is these architectures are evolving alongside these new markets, and it isn't always clear how data will move across these chips, between devices, and between systems. Chip architectures are becom... » read more

Closing Functional And Structural Coverage On RTL Generated By High-Level Synthesis


Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to clos... » read more

Blog Review: Mar. 13


Mentor's Tom Fitzpatrick questions whether deep learning approaches can really help improve coverage in modern, complex designs. Cadence's Paul McLellan listens in at MWC as Huawei chairman Guo Ping defends the company's security practices and shows where its heading in 5G. Synopsys' Eric Huang checks out the newly announced USB4 specification, changes to previous USB names, and a few things ... » read more

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