tag: Mentor

Week In Review: Design, Low Power
By Jesse Allen - 12 Oct, 2018 - Comments: 0

Deals AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP's FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories. Phison, a maker of NAND flash controller ICs, inked�... » read more

ML Becomes Useful For Variation Coverage
By Ann Mutschler - 11 Oct, 2018 - Comments: 0

According to industry sources, it is quite a feat to get a chip back from the foundry that actually meets the specifications the design team worked towards, and because of this much effort is underway across the industry to understand what will happen to a design once it reaches the manufacturing stage, and what the effects of design choices actually are. AI and ML are absolutely the buzz wo... » read more

Re-using Common Simulation Set-Up Processes To Speed Regression
By Rohit Jain - 11 Oct, 2018 - Comments: 0

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Power Delivery Affecting Performance At 7nm
By Brian Bailey - 11 Oct, 2018 - Comments: 4

Complex interactions and dependencies at 7nm and beyond can create unexpected performance drops in chips that cannot always be caught by signoff tools. This isn't for lack of effort. The amount of time spent trying to determine if an advanced-node chip will work after it is fabricated has been rising steadily for several process nodes. Additional design rules handle everything from variation... » read more

Power Issues Grow For Cloud Chips
By Ann Mutschler - 11 Oct, 2018 - Comments: 0

Performance levels in traditional or hyperscale data centers are being limited by power and heat caused by an increasing number of processors, memory, disk and operating systems within servers. The problem is so complex and intertwined, though, that solving it requires a series of steps that hopefully add up to a significant reduction across a system. But at 7nm and below, predicting exactly... » read more

Boosting Regression Throughput By Reusing Setup Phase Simulation
By Mentor, a Siemens Business - 10 Oct, 2018 - Comments: 0

This paper discusses how to write a design so the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. It also discusses what type of designs are appropriate for this methodology and what a designer can do to make his/her design suitable for it. Also c... » read more

Blog Review: Oct. 10
By Jesse Allen - 10 Oct, 2018 - Comments: 0

In a video, Cadence's Megha Daga dives into sparsity in neural networks and how it affects bandwidth, performance, and power efficiency. In a video, Mentor's Colin Walls takes a look at efficient embedded code, and why that means different things at different times. Synopsys' Eric Huang argues that in the realm of video standards, HDMI, DisplayPort, and USB Type-C are set to continue comp... » read more

Automakers Take On More Responsibility
By Kevin Fogarty - 08 Oct, 2018 - Comments: 0

Chip and EDA companies are scrambling to deal with stiff safety regulations and harsh environmental conditions for automotive chips, but automakers are making big changes of their own to ensure all those components work together as expected. The result is a significant shift of responsibilities of companies in the automotive supply chain. Carmakers traditionally have left verification, valid... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology
By Mentor, a Siemens Business - 08 Oct, 2018 - Comments: 0

This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

So Many Waivers Hiding Issues
By Brian Bailey - 05 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

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