tag: Mentor

Week In Review: Design, Low Power
By Jesse Allen - 05 Oct, 2018 - Comments: 0

Mirabilis Design debuted an AI-driven tool for performance analysis and architecture exploration of SoCs and embedded systems. VisualSim AI Processor Generator creates pipeline-accurate models that have port integration with standard buses and memories, which is used to compare different processor families, optimize the specification and identify system bottlenecks. The generated model supports... » read more

Autonomous Vehicles: IC Design Flow Walk Through
By Andrew Macleod - 04 Oct, 2018 - Comments: 0

Automotive applications, particularly those related to AI and computer vision, are a significant driver of the current semiconductor boom. Established companies are mostly thriving, it’s true, but perhaps more interesting are all the new faces in the game. As usual, Mentor CEO Wally Rhines is one of the great sense-makers of the all this activity. Wally has been making the rounds at variou... » read more

Adding Safety Into Automotive Design
By Ann Mutschler - 04 Oct, 2018 - Comments: 0

The ISO 26262 spec is a household term for anyone even remotely involved with the automotive industry today. Increasingly, though, it is being used interchangeably with safety-readiness across the entire supply chain. ISO 26262 compliance is a prerequisite for IP and chips used in an increasing number of automotive applications. It applies to systems, software, and to individual products. An... » read more

Making Buildings Smarter
By Jeff Dorsch - 04 Oct, 2018 - Comments: 1

Calling a building “smart” implies that technology is embedded to make that building more efficient, useful, convenient and profitable. The goal is to program efficiency beyond what humans can provide. But “smart” also may imply a healthy dose of marketing hype. No one wants to live in a “dumb building,” but it's difficult to define what makes a building smart. And while much is ... » read more

Cloud Drives Changes In Network Chip Architectures
By Ann Mutschler - 03 Oct, 2018 - Comments: 0

Cloud data centers have changed the networking topology and how data moves throughout a large data center, prompting significant changes in the architecture of the chips used to route that data and raising a whole new set of design challenges. Cloud computing has emerged as the fast growing segment of the data center market. In fact, it is expected to grow three-fold in the next few years, a... » read more

Blog Review: Oct. 3
By Jesse Allen - 03 Oct, 2018 - Comments: 0

Applied's Buvna Ayyagari-Sangamalli notes that the requirements of AI are challenging the entire design ecosystem, and while new materials are necessary, so is keeping up the current pace of architecture and EDA development. Mentor's Joe Hupcey III digs into how to handle counters effectively with formal by reducing their size or replacing them with abstract models to allow formal engines to... » read more

Proof-Of-Concept To Product: Initial Design Of A MEMS Sensor
By Mentor, a Siemens Business - 03 Oct, 2018 - Comments: 0

In previous papers, we have covered how to design and verify an IoT tank fluid-level monitoring system. We covered how to create a proof-of-concept and prototype. In this series of white papers, we explore the detailed product design of the MEMS pressure sensor within this system. In this initial whitepaper, we introduce the piezoelectric micro-machined ultrasonic transducer (PMUT) sensor, show... » read more

EDA, IP Revenues Up Again
By Ed Sperling - 01 Oct, 2018 - Comments: 0

EDA and IP revenues were up across the board yet again, buoyed by growth across a number of new markets and an increase in new and existing companies developing chips for those markets. All told, revenue grew to $2.39 billion in Q2 of 2018, an 8.2% increase over the $2.21 billion reported in the same period in 2017, according to numbers released today by the ESD Alliance's Market Statistics ... » read more

RISC-V Inches Toward The Center
By Ann Mutschler - 01 Oct, 2018 - Comments: 1

RISC-V is pushing further into the mainstream, showing up across a wide swath of designs and garnering support from a long and still-growing list of chipmakers, tools vendors, universities and foundries. In most cases it is being used as a complementary processor than a replacement for something else, but that could change in the future. What makes RISC-V particularly attractive to chipmaker... » read more

Next-Generation Liberty Verification And Debugging
By WeiLii Tan - 27 Sep, 2018 - Comments: 1

Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

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