Week in Review: IoT, Security, Auto


Internet of Things NXP Semiconductors provided its A71CH trust anchor to Google IoT Cloud, enabling authentication for Google IoT Cloud Core. The technology helps to secure edge devices for Internet of Things deployments. Separately, NXP announced the promotion of Kurt Sievers, executive vice president and general manager of the chip company’s automotive business, to president of NXP Semicon... » read more

Solving Puzzling Power-Aware Coverage: Getting An Aggregated Coverage Metric


Coverage metrics tell us when a design has been thoroughly verified, or at least exercised to the point of diminishing returns. Rarely can every design artifact or design parameter of a highly complex design be covered 100 percent, but we can use coverage metrics to know the extent to which we have verified the design — enough to be confident that it will function as desired in the end produc... » read more

Enabling Cheaper Design


While the EDA industry tends to focus on cutting edge designs, where design costs are a minor portion of the total cost of product, the electronics industry has a very long tail. The further along the tail you go, the more significant design costs become as a percent of total cost. Many of those designs are traditionally built using standard parts, such as microcontrollers, but as additional... » read more

Process Corner Explosion


The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

Minimizing Chip Aging Effects


Aging kills semiconductors, and it is a growing problem for an increasing number of semiconductor applications—especially as they migrate to more advanced nodes. Additional analysis and prevention methods are becoming necessary for safety critical applications. While some aspects of aging can be mitigated up front, others are tied to the operation of the device. What can an engineering tea... » read more

Low Power Coverage: The Missing Piece In Dynamic Simulation


Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

People Vs. Self-Driving Cars


If you’re a screenwriter—or a car salesman—you’re already thinking of ways to write non-sci-fi self-driving cars into a movie script. Automobiles have been integral to the plots of gritty noir crime movies, heist flicks, romantic comedies, and obviously, road movies. What's clear is the self-driving car won’t be the ideal getaway vehicle anymore, particularly if there is no steerin... » read more

Blog Review: Sept. 12


Cadence's Paul McLellan checks out the impact the Meltdown, Spectre, and Foreshadow vulnerabilities will have on future processor design with an overview of speculative execution and why it's important to current architectures. Mentor's Matthew Ballance suggests some ways to find existing information and descriptions that can be used to jump-start the creation of portable stimulus models. ... » read more

The Race To Zero Defects


By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

Tessent Cell-Aware Test


Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

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