tag: Mentor

When Bugs Escape
By Brian Bailey - 26 Jul, 2018 - Comments: 0

Bugs are a fact of life, and they always have been. But verification methodologies may not have evolved fast enough to keep up with the growing size and complexity of systems. The types of bugs are changing, too. Some people call these corner cases. Others call them outliers. Still another group refers to them as simulation-resistance superbugs. In markets such as automotive, the notion o... » read more

Synthesizing Computer Vision Designs To Hardware
By Mike Fingeroff - 26 Jul, 2018 - Comments: 0

Computer vision is one of the hottest markets in electronic design today. Digital processing of images and video with complex algorithms in order to interpret meaning has almost as many applications and markets as there are uses for the human eye. The biggest problem that designers face is that the computer vision system requirements and algorithms change quickly and often. Even the targ... » read more

Accelerate Computer Vision Design Using High-Level Synthesis
By Mentor, a Siemens Business - 25 Jul, 2018 - Comments: 0

Computer vision solutions are all around us, in cars, consumer products, security, retail, and agriculture. But, designing these solutions is not easy, mainly because of constant algorithm upgrades and related requirements changes. This means that wherever the team is in the RTL creation and verification flow, they might have to start over, which can cause an unacceptable delay in the productio... » read more

Blog Review: July 25
By Jesse Allen - 25 Jul, 2018 - Comments: 0

Mentor's Daniel Clarke takes a look at some of the challenges to effective sensor fusion in automotive and why it's important to develop different sensing methodologies for particular driving tasks and levels of automation. Cadence's Meera Collier explains the evolution in wireless networks that's brought us to 5G and why it will be such a big deal for a massively connected world. Synopsy... » read more

Verification As A Flow (Part 3)
By Brian Bailey - 24 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Safety, Security And PPA Tradeoffs
By Brian Bailey - 23 Jul, 2018 - Comments: 0

Safety and security are emerging as key design tradeoffs as chips are added into safety-critical markets, adding even more complexity into an already complicated optimization process. In the early days of semiconductor design, performance and area were traded off against each other. Then power became important, and the main tradeoffs became power, performance and area (PPA). But as chips inc... » read more

Blog Review: July 18
By Jesse Allen - 18 Jul, 2018 - Comments: 0

Synopsys' Shivani Bansal introduces DFI 5.0, the latest interface specification that defines signals, timing, and functionality required for efficient communication between the memory controller and PHY, including changes to boost performance in DDR5/LPDDR5. Mentor's Ricardo Anguiano contends that for greater autonomy in vehicles, centralized sensor fusion is necessary to both reduce the cos... » read more

Power-Aware Static Checks: Static Checker Results And Debugging Techniques
By Progyna Khondkar - 17 Jul, 2018 - Comments: 0

In Part 1 of this three article series on power aware (PA) verification, we examined the foundations and verification features of PA static checks. In Part 2, we discussed the features of the static verification library and described best static verification practices. Part 3 concludes this series with details of static PA verification tool procedures using a real example to analyze PA-Stati... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Low Power Coverage
By Mentor, a Siemens Business - 16 Jul, 2018 - Comments: 0

Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy