tag: Mentor

Process Variation Not A Solved Issue
By Ann Mutschler - 09 Aug, 2018 - Comments: 4

Semiconductor Engineering sat down to talk about process variation in advanced nodes, and how design teams are coping, with Christoph Sohrmann, a member of the Advanced Physical Verification group in Fraunhofer’s Division of Engineering of Adaptive Systems (EAS); Juan Rey, vice president of engineering at Mentor, A Siemens Business; and Stephen Crosher, CEO of Moortec Semiconductor. What foll... » read more

Utilizing Clock-Gating Efficiency To Reduce Power In RTL Designs
By Mentor, a Siemens Business - 08 Aug, 2018 - Comments: 0

With the advent of the consumer era and the popularity of mobile applications, power optimization is the mantra of the day. Designers go through several iterations to optimize power in order to achieve their power budgets. The average Clock-Gating Efficiency for a design is a much better indicator of dynamic power consumption because it is a measure of both how many and how long registers are g... » read more

Blog Review: Aug. 8
By Jesse Allen - 08 Aug, 2018 - Comments: 0

Cadence's Meera Collier provides a primer on the basics of quantum computing, including how quantum gates work using superpositions and how it could impact chip design. Mentor's Dennis Brophy shares a list of resources to help you get up to speed on the recently-approved Portable Test and Stimulus standard, which enables test scenarios to be run across different execution platforms. Synop... » read more

The Chiplet Race Begins
By Mark LaPedus - 06 Aug, 2018 - Comments: 1

Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

More Sigmas In Auto Chips
By Ann Mutschler - 02 Aug, 2018 - Comments: 0

The journey to autonomous cars is forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. This includes everything from new requirements for automotive-grade chips to longer mean time between failures. But it also makes it far more challenging, time-consuming and complicated to create these d... » read more

Smart Cities’ Head Start On The Mobility Future
By Andrew Macleod - 02 Aug, 2018 - Comments: 0

Even if autonomy is still mostly in the R&D, balky-science-project phase, vehicle connectivity is increasingly here today. And that’s good news since connected cars deliver a meaningful subset of the societal upside promised by their eventual fully autonomous future selves, especially when it comes to safety, traffic management and navigation. But beyond the dashboard, as the world become... » read more

How Vehicle Electrification Impacts Electrical System Design
By Mentor, a Siemens Business - 01 Aug, 2018 - Comments: 0

Autonomy and electrification are demanding significant changes to electrical and electronic architectures within vehicles. This is due in part to the introduction of high voltages, increased safety considerations and significant weight reductions needed to maximize vehicle range from electrification, and ‘fail operational’ designs, hugely increased data network loading and virtual validatio... » read more

Blog Review: Aug. 1
By Jesse Allen - 01 Aug, 2018 - Comments: 0

Synopsys' Taylor Armerding explains the recent cyberattack on Singapore's largest healthcare group, SingHealth. The "well-planned" attack compromised the personal information of about a quarter of the country's population, including Prime Minister Lee Hsien Loong. Cadence's Paul McLellan looks at the factors that make China's automotive market much different from the rest of the world and th... » read more

Why Parallelization Is So Hard
By Brian Bailey - 30 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Debug Issues Grow At New Nodes
By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

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