tag: Mentor

Big Changes For Mainstream Chip Architectures
By Ed Sperling - 23 Aug, 2018 - Comments: 3

Chipmakers are working on new architectures that significantly increase the amount of data that can be processed per watt and per clock cycle, setting the stage for one of the biggest shifts in chip architectures in decades. All of the major chipmakers and systems vendors are changing direction, setting off an architectural race that includes everything from how data is read and written in m... » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 22 Aug, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Blog Review: Aug. 22
By Jesse Allen - 22 Aug, 2018 - Comments: 0

Cadence's Paul McLellan considers how much further we need to go to make EUV work for 5nm, the problem of cost, and ASML's EUV roadmap. In a video, Mentor's Colin Walls explains optimizing data in embedded software with a simple example of two ways to put data in memory and how to decide which is best. Synopsys' Fred Bals provides a rundown of the different types of application security t... » read more

Big Shifts In Tech Conferences
By Ed Sperling - 16 Aug, 2018 - Comments: 0

By Ed Sperling and Katherine Derbyshire Identifying central themes in technology conferences, or finding enough latitude where the theme is extremely well defined, is becoming challenging throughout the tech industry. Throughout the semiconductor industry, in particular, many are asking how various organizations will differentiate conferences in the future and who will be the target audience... » read more

Blog Review: Aug. 15
By Jesse Allen - 15 Aug, 2018 - Comments: 0

Cadence's Paul McLellan checks out what's driving the growth of China's semiconductor industry plus the state of fab construction, from a CAPSA presentation by SEMI's Lung Chu. Mentor's Joe Hupcey III has some tips for how to handle inconclusive results in formal verification, starting with how to identify where the analysis got stuck. Synopsys' Taylor Armerding listens in on a presentati... » read more

Do Parallel Tools Make Sense?
By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Week in Review: IoT, Security, Auto
By Jeff Dorsch - 10 Aug, 2018 - Comments: 0

Cybersecurity Jens (Atom) Steube, a cybersecurity researcher and creator of the Hashcat password cracking tool, was probing for vulnerabilities in the new WPA3 security standard for Wi-Fi routers. WPA3 presents a robust defense against hacking, yet Steube discovered a security flaw in routers using WPA/WPA2 – one that leaves Wi-Fi passwords enabled with Pairwise Master Key Identifiers vulner... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Aug, 2018 - Comments: 0

Achronix and Mentor uncorked an optimized HLS flow for Achronix's FPGA technology products. The integrated development environment enables designers to quickly go from C++ to FPGA using Mentor's Catapult HLS and Achronix's ACE design tools. Initially used for 5G wireless applications to reduce the overall development effort and improve QoR, it is suitable for any design targeting Achronix techn... » read more

Chip Aging Becomes Design Problem
By Brian Bailey - 09 Aug, 2018 - Comments: 9

Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation
By Tom Fitzpatrick - 09 Aug, 2018 - Comments: 0

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’... » read more

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