tag: Mentor

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Verification As A Flow (Part 1)
By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 4
By Jesse Allen - 04 Jul, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to get the full benefits of AI, new computing architectures are needed – and that will require new breakthroughs in materials engineering to get beyond classic 2D scaling. Cadence's Tom Wong considers to what extent chip dis-integration is happening and how the industry can cope with the escalating costs of new process nodes and higher-speed i... » read more

The Darker Side Of Consolidation
By Ed Sperling - 02 Jul, 2018 - Comments: 1

Another wave of consolidation is underway in the semiconductor industry, setting the stage for some high-stakes competitive battles over market turf and sowing confusion across the supply chain about continued support throughout a product's projected lifetime. The consolidation comes as chipmakers already are grappling with rising complexity, the loss of a roadmap for future designs as Moore... » read more

Week in Review: IoT, Auto, Security
By Jeff Dorsch - 29 Jun, 2018 - Comments: 0

Executive Changes Rambus' board of directors named Luc Seraphin, senior vice president and general manager of the company's Memory and Interfaces Division, as interim CEO while it searches for a replacement for Ron Black. The board terminated Black this week, saying the reason for termination did not involve Rambus' financial and business performance. The company also named Mike Noonen as se... » read more

Week In Review: Design, Low Power
By Jesse Allen - 29 Jun, 2018 - Comments: 0

M&A Siemens acquired Austemper Design Systems, which provides tools for functional safety and safety-critical designs. Founded in 2015, Texas-based Austemper adds state-of-the-art safety analysis, auto-correction and fault simulation technology to address random hardware faults, as well as correct and harden vulnerable areas, subsequently performing fault simulation to ensure the design is... » read more

Wednesday At DAC 2018
By Brian Bailey - 28 Jun, 2018 - Comments: 0

Wednesday starts with a visionary talk followed by a keynote. The Visionary talk was given by Chidi Chidambaram, VP of engineering for Qualcomm, and looked at 'Challenges to Enable 5G System Scaling.' "We have to start taking a system view rather than just following technology and at the same time we have to get concerned about durability," he said. "Mobile will continue to be the leader becaus... » read more

Raising The Bar On Flat CDC Verification With Hierarchical Data Models
By Ashish Hari - 28 Jun, 2018 - Comments: 0

By Ashish Hari, Aditya Vij, and Ping Yeung Traditionally, clock domain crossing (CDC) verification at the SoC level has relied on flat simulation runs. But flat CDC verification has run out of gas. Largely because of the increase in the number of asynchronous clocks in larger, faster, more complex designs. Flat CDC runs are too performance intensive, time-consuming, and result in high noise.... » read more

Searching For A System Abstraction
By Brian Bailey - 28 Jun, 2018 - Comments: 3

Without abstraction, advances in semiconductor design would have stalled decades ago and circuits would remain about the same size as analog blocks. No new abstractions have emerged since the 1990s that have found widespread adoption. The slack was taken up by IP and reuse, but IP blocks are becoming larger and more complex. Verification by isolation is no longer a viable strategy at the system... » read more

Comprehensive CDC Verification Using Advanced Hierarchical Data Models
By Mentor, a Siemens Business - 27 Jun, 2018 - Comments: 0

In this paper, we describe the hierarchical data model (HDM), which is a performance efficient alternative to the traditional flat CDC verification flow. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly re-used across releases and across designs wherever the IP i... » read more

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